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path: root/src/mem
AgeCommit message (Expand)Author
2013-03-15ruby: set: corrects csprintf() call introduced by 7d95b650c9b6Nilay Vaish
2013-03-07ruby: Fix gcc 4.8 maybe-uninitialized compilation errorAndreas Hansson
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-03-06ruby: garnet: fixed: implement functional accessNilay Vaish
2013-03-02ruby: fixes functional writes to RubyRequestBlake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-01mem: Add check if SimpleDRAM nextReqEvent is scheduledAndreas Hansson
2013-03-01mem: Add a method to build multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: SimpleDRAM variable naming and whitespace fixesAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-03-01mem: Merge interleaved ranges when creating backing storeAndreas Hansson
2013-03-01mem: Merge ranges in bus before passing them onAndreas Hansson
2013-02-28ruby: mesi coherence protocol: invalidate lockDibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-02-19slicc: remove unused variable message_buffer_namesNilay Vaish
2013-02-19ruby: remove unused variable m_print_config in class TopologyNilay Vaish
2013-02-19mem: Fix sender state bug and delay poppingAndreas Hansson
2013-02-19scons: Fix warnings issued by clang 3.2svn (XCode 4.6)Andreas Hansson
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-19mem: Ensure trace captures packet fields before forwardingAndreas Hansson
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-14Ruby: Fix compilation errors on gcc 4.7 and clang 3.2Andreas Hansson
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
2013-02-10ruby: enable multiple clock domainsNilay Vaish
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
2013-02-10ruby: replace Time with Cycles in garnet fixed and flexibleNilay Vaish
2013-02-10ruby: replace Time with Tick in replacement policy classesNilay Vaish
2013-02-10ruby: convert block size, memory size to unsignedNilay Vaish
2013-02-10ruby: replace Time with Cycles in MessageBufferNilay Vaish
2013-02-10ruby: replace Time with Cycles in Memory ControllerNilay Vaish
2013-02-10ruby: Replace Time with Cycles in SequencerMessageNilay Vaish
2013-02-10ruby: replace Time with Cycles in Message classNilay Vaish
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
2013-02-10ruby: modifies histogram add() functionNilay Vaish
2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
2013-01-31ruby: correct computation of number of bits required for addressNilay Vaish
2013-01-31mem: Add comments for the DRAM address decodingAndreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
2013-01-31mem: Separate out the different cases for DRAM bus busy timeAndreas Hansson
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-28ruby: remove get_time()Nilay Vaish
2013-01-28ruby: remove call to curCycle in panic()Nilay Vaish