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path: root/src/mem
AgeCommit message (Expand)Author
2014-09-01ruby: slicc: donot prefix machine name to variablesNilay Vaish
2014-09-01ruby: remove unused toString() from AbstractControllerNilay Vaish
2014-09-01ruby: network: move getNumNodes() to base classNilay Vaish
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-09-01ruby: move files from ruby/system to ruby/structuresNilay Vaish
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-04-01mem: adding a multi-level page table classAlexandru
2014-08-26mem: Fix DRAMSim2 cycle check when restoring from checkpointAndreas Hansson
2014-08-26mem: Update DRAM controller commentsAndreas Hansson
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson
2014-08-13mem: Properly set cache block status fields on writebacksMitch Hayenga
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-06-30mem: Add bank and rank indices as fields to the DRAM bankAndreas Hansson
2014-06-30mem: Extend DRAM row bits from 16 to 32 for larger densitiesAndreas Hansson
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23ruby: slicc: remove unused ids DNUCA*Nilay Vaish
2014-05-23ruby: remove old protocol documentationNilay Vaish
2014-05-23ruby: message buffer: drop dequeue_getDelayCycles()Nilay Vaish
2014-05-09mem: Update DDR3 and DDR4 based on datasheetsAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-05-09mem: Squash prefetch requests from downstream cachesMitch Hayenga
2014-05-09mem: Auto-generate CommMonitor trace file namesSascha Bischoff
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
2014-04-19ruby: slicc: remove old documentationNilay Vaish
2014-04-19ruby: slicc: slight change to rule for transitionsNilay Vaish
2014-04-19ruby: recorder: Fix (de-)serializing with different cache block-sizesMarco Elver
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
2014-03-23mem: Add close adaptive paging policy to DRAM controller modelWendy Elsasser
2014-03-23mem: DRAM controller tidying upAndreas Hansson
2014-03-23mem: Fix bug in DRAM bytes per activateAndreas Hansson
2014-03-23mem: Limit the accesses to a page before forcing a prechargeAndreas Hansson
2014-03-23mem: Make DRAM write queue draining more aggressiveAndreas Hansson
2014-03-23mem: DDR3 config for comparing with DRAMSim2Neha Agarwal
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson