gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-01	ruby: slicc: improve the grammar	Nilay Vaish
2014-09-01	ruby: mesi three level: slight naming changes.	Nilay Vaish
2014-09-01	ruby: slicc: donot prefix machine name to variables	Nilay Vaish
2014-09-01	ruby: remove unused toString() from AbstractController	Nilay Vaish
2014-09-01	ruby: network: move getNumNodes() to base class	Nilay Vaish
2014-09-01	ruby: eliminate type Time	Nilay Vaish
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish
2014-08-28	mem: adding architectural page table support for SE mode	Alexandru
2014-04-01	mem: adding a multi-level page table class	Alexandru
2014-08-26	mem: Fix DRAMSim2 cycle check when restoring from checkpoint	Andreas Hansson
2014-08-26	mem: Update DRAM controller comments	Andreas Hansson
2014-08-26	mem: Fix address interleaving bug in DRAM controller	Andreas Hansson
2014-08-13	mem: Properly set cache block status fields on writebacks	Mitch Hayenga
2014-07-28	mem: refactor LRU cache tags and add random replacement tags	Anthony Gutierrez
2014-06-30	mem: DRAMPower trace output	Andreas Hansson
2014-06-30	mem: Add bank and rank indices as fields to the DRAM bank	Andreas Hansson
2014-06-30	mem: Extend DRAM row bits from 16 to 32 for larger densities	Andreas Hansson
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-05-23	ruby: slicc: remove unused ids DNUCA*	Nilay Vaish
2014-05-23	ruby: remove old protocol documentation	Nilay Vaish
2014-05-23	ruby: message buffer: drop dequeue_getDelayCycles()	Nilay Vaish
2014-05-09	mem: Update DDR3 and DDR4 based on datasheets	Andreas Hansson
2014-05-09	mem: Add DRAM cycle time	Andreas Hansson
2014-05-09	mem: Simplify DRAM response scheduling	Andreas Hansson
2014-05-09	mem: Add precharge all (PREA) to the DRAM controller	Andreas Hansson
2014-05-09	mem: Remove printing of DRAM params	Andreas Hansson
2014-05-09	mem: Add tRTP to the DRAM controller	Andreas Hansson
2014-05-09	mem: Merge DRAM latency calculation and bank state update	Andreas Hansson
2014-05-09	mem: Add tWR to DRAM activate and precharge constraints	Andreas Hansson
2014-05-09	mem: Merge DRAM page-management calculations	Andreas Hansson
2014-05-09	mem: Add DRAM power states to the controller	Andreas Hansson
2014-05-09	mem: Ensure DRAM refresh respects timings	Andreas Hansson
2014-05-09	mem: Make DRAM read/write switching less conservative	Andreas Hansson
2014-05-09	mem: Squash prefetch requests from downstream caches	Mitch Hayenga
2014-05-09	mem: Auto-generate CommMonitor trace file names	Sascha Bischoff
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-04-19	ruby: slicc: remove old documentation	Nilay Vaish
2014-04-19	ruby: slicc: slight change to rule for transitions	Nilay Vaish
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-04-08	ruby: slicc: change enqueue statement	Nilay Vaish
2014-04-08	ruby: coherence protocols: drop the phrase IntraChip	Nilay Vaish
2014-03-23	mem: Track DRAM read/write switching and add hysteresis	Andreas Hansson
2014-03-23	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	Andreas Hansson
2014-03-23	mem: Change memory defaults to be more representative	Andreas Hansson
2014-03-23	mem: Add close adaptive paging policy to DRAM controller model	Wendy Elsasser
2014-03-23	mem: DRAM controller tidying up	Andreas Hansson
2014-03-23	mem: Fix bug in DRAM bytes per activate	Andreas Hansson
2014-03-23	mem: Limit the accesses to a page before forcing a precharge	Andreas Hansson
2014-03-23	mem: Make DRAM write queue draining more aggressive	Andreas Hansson
2014-03-23	mem: DDR3 config for comparing with DRAMSim2	Neha Agarwal