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2019-05-08mem-cache: Create cache compressorDaniel R. Carvalho
Create basic template for cache compressors. A basic compressor must implement a compression and a decompression method. Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add block size to findVictimDaniel R. Carvalho
Add block size to findVictim. For standard caches it will not be used. Compressed caches, however, need to know the size of the compressed block to decide whether a block is co-allocatable or not. Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression data to CompressionBlkDaniel R. Carvalho
Add a compression bit, decompression latency and compressed block size and their respective getters and setters. Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create CacheComp debug flagDaniel R. Carvalho
Create a debug flag for cache compression. Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-08mem-cache: Stub compression frameworkDaniel R. Carvalho
Create a stub of a compression framework where we can have multiple data blocks per tag entry. Only consecutive blocks can share a tag as of now. For each tag entry there can be multiple data blocks. We have the same number of tags a conventional cache would have, but we instantiate the maximum number of data blocks (according to the compression ratio) per tag, to virtually implement compression without increasing the complexity of the simulator. Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-03mem-cache: Mark block as dirty after a SWPrefetchEXRespNikos Nikoleris
This is a workaround for a bug introduced from the change: 59e3585a8 arch-arm: We add PRFM PST instruction for arm which can cause deadlocks in the memory system. The design of the classic memory system in gem5 makes the folloing two assumptions: * A cache that fetches a block with an intention to modify it, becomes the point of ordering and therefore commits to respond to any snoop requests [1]. * A cache that fetches an exclusive copy of the block, does so with the intention to modify it [2]. Immediately after it receives the block, it will write to it and mark it as dirty. As the point of ordering, it responds to any outstanding snoops. The current implementation of prefetch exclusive request breaks the second assumption. A cache can fetch an exclusive block without an immediate intention to modify it. If the block is not modified, it will not be marked as dirty. However, the cache has committed to respond to outstanding snoops, and if the block is clean it won't. This can result in deadlocks where a snoop gets stuck waiting for responses. One solution (implemented by this patch) is to unconditionally mark the block dirty when filling due to a prefetch exclusive request. This makes the PrefetchExReq behave like a WriteReq. However, as it may mark as dirty a clean block, it creates the requirement for an uncessary WritebackDirty in the future. In practice, this shouldn't be a big problem unless the application is unnecessarily using prefetch exclusive instructions. Other solutions, would require deeper changes to the design of the memory system to handle this properly. [1]: When a cache commits to respond, it "informs" the xbar/PoC (point of coherence) and the other caches of its intention to respond. As a result the request will not be send to the main memory. [2]: In fact the assumption is that in the needsWritable MSHR there is at least one WriteReq before any snoops from other caches. Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17729 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
Change-Id: I731d3ef021596450ac307461f215760a148bb28a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
This changeset enables clone to work with X86KvmCPU model, which will allow running multi-threaded applications at near hardware speeds. Even though the application is multi-threaded, the KvmCPU model uses one event queue, therefore, only one hardware thread will be used, through KVM, to simulate multiple application threads. Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22mem-cache: Fix fix of replacement countDaniel
Commit 7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing replacement update when a single location can be associated to multiple blocks. Although the comment of the correct action was added, the proper validation check was forgotten. This change adds that check and moves doing the eviction to when there is a valid block. Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-19mem-cache: Fix increasing replacement countDaniel R. Carvalho
Replacements should be increased when there is any evicted block, which does not necessarily have to be the victim. For example, assume a superblock contains 4 blocks, and both A and C are stored compressed (belonging to SB_1). Then F, from SB2 needs to make room by replacing SB1. If F map to location 2, the number of replacements should be increased, even though 2 had no valid blocks: Tag Data Tag Data |SB_1|--|A|X|C|X| --> |SB_2| |X|F|X|X| 1 2 3 4 1 2 3 4 Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-19mem-cache: Remove blk_addr from Queue::trySatisfyFunctionalDaniel R. Carvalho
The blk_addr is pkt->getBlockAddr(), and therefore can be acquired internally, when needed, as long as the pkt is provided. Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Add match functions to QueueEntryDaniel R. Carvalho
Having the caller decide the matching logic is error-prone, and frequently ends up with the secure bit being forgotten. This change adds matching functions to the QueueEntry to avoid this problem. As a side effect the signature of findPending has been changed. Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Add packet matching functionsDaniel R. Carvalho
Add both block and non-block-aligned packet matching functions, so that both address and secure bits are checked when checking whether a packet matches a request. Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Move Target to QueueEntryDaniel R. Carvalho
WriteQueueEntry's target has 100% functionality overlap with MSHR's, therefore make it base to MSHR::Target. Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem-cache: Assert Entry inherits from QueueEntry in QueueDaniel R. Carvalho
Queue has several assumptions regarding its template parameter, so make sure they are fulfilled by forcing Entry to be derived from QueueEntry. Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
DRAMCtrl's decodeAddr does not need to modify the packet it receives, nor should it modify the contents of the class, and therefore both the packet and the function are made const. Change-Id: I577f48d9a43611ba54878a9a793cb7b4fbb326f4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17540 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19mem: Allow packet to provide its own addr rangeDaniel R. Carvalho
Add a getter to Packet to allow it to provide its own addr range. Change-Id: I2128ea3b71906502d10d9376b050a62407defd23 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17536 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-16mem: missing override specifierAndrea Mondelli
Change-Id: Ied4817bcda317826303a1bb688b41823b18b489b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18128 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-14mem: Teach SimpleMem to return a MemBackdoor when appropriate.Gabe Black
If the back door SimpleMem inherits from AbstractMem has a pointer and is hence valid, SimpleMem will return that pointer when asked. Change-Id: I734daba48e4ae5b4ad8ac9a108e7b12b5e82803f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17669 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-14mem: Maintain a back door into the AbstractMem's backing store.Gabe Black
The backing store pointer is added to the back door when it's set, assuming that the range isn't interleaved. If it is interleaved, then there isn't a way to get a flat pointer to the backing store. Depending on how the backing store is set up, it may be possible to return a larger backdoor which applies to all interleaved memories at the same time and to avoid problems with interleaving. I'm leaving this as a todo. Change-Id: I0e531c22835ec10954ab39f761b3d87666b59220 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17668 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-11mem-cache: Fix RRPV for RRIPAnis Peysieux
The RRPV values for RRIP and NRU replacment policies. Long re-rereference interval was used instead of distant re-rereference interval and vice-versa. The btp value permit to choose beetwen distant and long insertion ratio. A btp value of 0 force the policy to always insert at a distant re-reference interval and a btp value of 100 force the policy to always insert at a long (intermediate) re-rereference interval. Change-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-10mem: Plumb backdoor requests through the xbar classes.Gabe Black
Change-Id: Ic8f49339ab95c31d2f00edfdf23a46f1271ec3aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17593 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-10mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.Gabe Black
These both perform atomic accesses like their non-backdoor equivalents, and also request a backdoor corresponding to the access. The default implementation for recvAtomicBackdoor prints a warning (once per port instance), calls recvAtomic to do the actual access, and leaves the backdoor pointer as nullptr. That way if an object doesn't know how to handle or transfer requests for a back door, it automatically replies in a safe way that ignores the back door request. Change-Id: Ia9fbbe9996eb4b71ea62214d203aa039a05f1618 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17590 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-10mem-cache: Fix MSHR handling of cache clean requestsNikos Nikoleris
Previously satisfied clean requests would not snoop in-service MSHRs. This is a problem when a clean request is also invalidating, in which case we have to post-invalidate or post-downgrade outstanding requests. This changes fixes this bug. Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-04-06mem: Add a MemBackdoor type to track memory backdoors.Gabe Black
These are similar to the structures TLM's DMI mechanism uses. Instead of having an invalidation broadcast which propogates backwards up the port hierarchy, this mechanism tracks a set of callbacks which are triggered when a back door is invalidated to let other holders clean up their bookkeeping. Change-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-05mem-cache: ambiguous use of abs functionRyan Gambord
std::abs doesn't accept unsigned long long, generating the error: error: call to 'abs' is ambiguous Use instead a compare-and-subtract idiom. Also, Changed return type of distanceFromTrigger from unsigned int to Addr to prevent overflow problems. Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-05mem: Reverse order of write/read mem queue checkJason Lowe-Power
For atomic RMW instructions that go directly to memory, we want to put them on the write queue instead of the read queue. Swap the if/else condition to accomplish this. Note: This is ignoring the read latency of the RMW, but these instructions should usually be handled in caches anyway. Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-04mem-cache: AMPM Prefetcher fails when restoring from a checkpointJavier Bueno
The preriodic event triggers an assertion due to an incorrect tick value to schedule when restoring from a checkpoint. Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: Fix PIF prefetcher compilation error with NULL ISAJavier Bueno
Referencing BaseCPU is causing a compilation error when using the NULL ISA. This patch changes the reference to a SimObject, which fixes the problem. Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: ISB prefetcher was triggering an assertionJavier Bueno
An assertion ignored the case when an entry of the SP table had been invalidated. Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-03mem-cache: Fix panic in Indirect Memory prefetcherJavier Bueno
Memory requests with a size non-power-of-two and less than 8 values were causing a panic, but there these should be allowed and ignored by the prefetcher. Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-02mem-cache: Proactive Instruction Fetch ImplementationIvan Pizarro
Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-28mem-cache: Remove extra cache header from AMAPDaniel R. Carvalho
The cache header was being included in the AMAP, although not used, which resulted in slightly longer compilation time. Change-Id: I3654bc719c6b5f558af116addae159301602a3cf Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711 Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-26mem: Deleting this init() method was accidentally dropped during rebase.Gabe Black
Deleting this init() method was part of a change just committed, but was accidentally dropped during a rebase. Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26mem: Clean up the xbars a little.Gabe Black
Get rid of comments which just restate the code, get rid of redundant "virtual" keywords, add "override"s, fix style, and get rid of xbar::init which was empty and hiding the parent class init. Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-20mem-cache: Added the STeMS prefetcherJavier Bueno
Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18mem-cache: tautological comparison of byteOrderAndrea Mondelli
Error: build/X86/mem/cache/prefetch/indirect_memory.cc:56:24: error: result of comparison of constant -1 with expression of type 'const ByteOrder' is always false [-Werror,-Wtautological-constant-out-of-range-compare] fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n"); ~~~~~~~~~ ^ ~~ build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if' if ((cond)) { \ ^~~~ 1 error generated. Fix: cast of constant (-1) used in comparison Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Removed circular include refRyan Gambord
If BasicLink.hh is modified, the style checker forces a reordering of the includes, which results in build errors because it ends up including Topology.hh before including its xxxParams.hh files, which include forward declarations of the BasicLink family of classes, and so Topology.hh throws errors that BasicLink etc. are not declared. Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem-cache: Added the Indirect Memory PrefetcherJavier Bueno
Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Move the Port base class into sim.Gabe Black
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15mem: Track the MemObject owner in MasterPort and SlavePort.Gabe Black
These types are much more tied to MemObjects and the gem5 memory protocol than the Port or BaseMasterPort and BaseSlavePort classes. Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15mem-cache: Fix write hit latency calculation orderDaniel
Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order at which the access latency is calculated for hits. This order is incorrect, since the calculations must use the blk's whenReady value before the access is satisfied. Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-12mem-cache: Removed default arg from get() in prefetch/base.hhRyan Gambord
commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Removal of default argument in src/mem/cache/prefetch/base.hh fixes this. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-11mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"Daniel R. Carvalho
Reverting patch due to polymorphism limitations. This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb. Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-10mem-cache: Added extra information to PrefetchInfoJavier Bueno
Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-31 17:25:59 +0000