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AgeCommit message (Expand)Author
2006-08-22Still need LL/SC support in cache, add hack to always return success for nowRon Dreslinski
2006-08-22Commiting a version of the multi-phase snoop atomic bus so people can see the...Ron Dreslinski
2006-08-21Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-21Changes so that time in the packet is actually set properly.Ron Dreslinski
2006-08-17Changes to build m5.fastSteve Reinhardt
2006-08-16DRAM Memory doesn't crash the simulator now.. still untested.Ali Saidi
2006-08-16Merge zizzer:/bk/newmemAli Saidi
2006-08-16Fix Physical Memory to allow memory sizes bigger than 128MB.Ali Saidi
2006-08-16Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-16Fixes for blocking in the caches that needed to be pulledRon Dreslinski
2006-08-15Merge zizzer:/bk/newmemAli Saidi
2006-08-15fixes for gcc 4.1Ali Saidi
2006-08-15Pulled out changes to fix EIO programs with caches. Also fixes any translati...Ron Dreslinski
2006-08-15Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-08-15Some changes to support blocking in the cachesRon Dreslinski
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-08-14Fix up doxygen.Steve Reinhardt
2006-08-14Changed the size parameter from int to int64_tGabe Black
2006-08-11#include of iostream needed.Gabe Black
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...Gabe Black
2006-07-20Move PioPort timing code into Simple Timing Port objectAli Saidi
2006-07-10Some fixes so that MSHR's are matched and we don't issue overlapping requests...Ron Dreslinski
2006-07-10Fix offset calculation. Now L2's work with timing&atomic.Ron Dreslinski
2006-07-07Fix address range calculation. Still need bus to handle snoop ranges.Ron Dreslinski
2006-07-07Update cpus to use the getPort function to use a connector object to connect ...Ron Dreslinski
2006-07-06Timing cache works for hello world test.Ron Dreslinski
2006-07-06Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-07-06Now timing reads work in single level of cache with simple cpuRon Dreslinski
2006-07-06Add default responder to busAli Saidi
2006-07-05Fix some unset values in the request in the timing CPU.Ron Dreslinski
2006-06-30AtomicSimpleCPU with a cache now runs the hello world! test program.Ron Dreslinski
2006-06-30First pass, now compiles with current head of tree.Ron Dreslinski
2006-06-30Fix the packet data allocation methods. Small fixes from changesets after my...Ron Dreslinski
2006-06-30Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-06-30All files compile in the mem directory except cache_builderRon Dreslinski
2006-06-29Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-06-29Still missing prefetch and tags directories as well as cache builder.Ron Dreslinski
2006-06-28More Changes, working towards cache.cc compiling. Headers cleaned up.Ron Dreslinski
2006-06-28Backing in more changsets, getting closer to compileRon Dreslinski
2006-06-28Was having difficulty with merging the cache, reverted to an early version an...Ron Dreslinski
2006-06-27change the page table from map to hash_map and create small cache to to speed...Ali Saidi
2006-06-26add syscall emulation page table fault so we can allocate more stack pagesAli Saidi
2006-06-25Allow ports to be created without a name.Kevin Lim
2006-06-17minor header cleanupsAli Saidi
2006-06-13Move SimObject creation and Port connection loopsSteve Reinhardt
2006-06-08add nacked result and a function to swizzle nacked packet into something that...Ali Saidi
2006-06-08add write/read functions that have endian conversions in themAli Saidi
2006-06-06Change ExecContext to ThreadContext. This is being renamed to differentiate ...Kevin Lim
2006-06-06Fix checker to work in newmem in SE mode.Kevin Lim
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