summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2014-01-04ruby: add support for clustersNilay Vaish
2014-01-04ruby: some small changesNilay Vaish
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
2013-12-20ruby: declare variables to be unsigned in Address.hhNilay Vaish
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-11-01mem: Fix DRAM bank occupancy for streaming accessAni Udipi
2013-11-01mem: Schedule time for DRAM event taking tRAS into accountAni Udipi
2013-11-01mem: Add tRAS parameter to the DRAM controller modelAni Udipi
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
2013-09-18mem: Fix scheduling bug in SimpleMemoryAndreas Hansson
2013-09-11ruby: Fix Topology throttle connectionsJoel Hestness
2013-09-11ruby: Statically allocate stats in SimpleNetwork, Switch, ThrottleJoel Hestness
2013-09-06ruby: network: convert to gem5 style statsNilay Vaish
2013-09-06ruby: profiler: removes function resourceUsage()Nilay Vaish
2013-09-06ruby: remove undefined message size typeNilay Vaish
2013-09-06ruby: network: removes reset functionalityNilay Vaish
2013-09-06ruby: network: shorten variable namesNilay Vaish
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-08-19stats: Cumulative stats updateAndreas Hansson
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-08-19mem: Warn instead of panic for tXAW violationAndreas Hansson
2013-08-19mem: Allow disabling of tXAW through a 0 activation limitAndreas Hansson