gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-08	mem: Make LL/SC locks fine grained	Mitch Hayenga
2013-01-08	mem: Fix use-after-free bug	Mitch Hayenga
2013-01-07	mem: Fix guest corruption when caches handle uncacheable accesses	Andreas Sandberg
2013-01-07	mem: Remove the IIC replacement policy	Andreas Sandberg
2013-01-07	sim: Fatal if a clocked object is set to have a clock of 0	Andreas Hansson
2013-01-07	mem: Merge ranges that are part of the conf table	Andreas Hansson
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2013-01-07	base: Simplify the AddrRangeMap by removing unused code	Andreas Hansson
2013-01-07	mem: Tidy up bus addr range debug messages	Andreas Hansson
2013-01-07	mem: Skip address mapper range checks to allow more flexibility	Andreas Hansson
2013-01-07	base: Encapsulate the underlying fields in AddrRange	Andreas Hansson
2013-01-07	mem: Remove the joining of neighbouring ranges	Andreas Hansson
2013-01-07	mem: Add tracing support in the communication monitor	Andreas Hansson
2013-01-07	mem: Add sanity check to packet queue size	Andreas Hansson
2013-01-07	ruby: Fix missing cxx_header in Switch	Andreas Hansson
2013-01-07	mem: Fix a bug in the memory serialization file naming	Andreas Hansson
2013-01-07	cache: add note about where conflicts are handled	Ali Saidi
2012-12-11	ruby: add support for prefetching to MESI protocol	Nilay Vaish
2012-12-11	ruby: change slicc to allow for constructor args	Nilay Vaish
2012-12-11	ruby: add a prefetcher	Nilay Vaish
2012-12-11	ruby: add functions for computing next stride/page address	Nilay Vaish
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-11-10	ruby: support functional accesses in garnet flexible network	Nilay Vaish
2012-11-10	ruby: bug in functionalRead, revert recent changes	Nilay Vaish
2012-11-08	mem: Fix DRAM draining to ensure write queue is empty	Andreas Hansson
2012-11-02	ruby: reset and dump stats along with reset of the system	Hamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-10-31	mem: Fix typo in port comments	Andreas Hansson
2012-10-25	dev: Make default clock more reasonable for system and devices	Andreas Hansson
2012-10-18	ruby: functional access updates to network test protocol	Nilay Vaish
2012-10-15	ruby: improved support for functional accesses	Nilay Vaish
2012-10-15	ruby: register multiple memory controllers	Nilay Vaish
2012-10-15	ruby: remove AbstractMemOrCache	Nilay Vaish
2012-10-15	ruby: allow function definition in slicc structs	Nilay Vaish
2012-10-15	ruby banked array: do away with event scheduling	Nilay Vaish
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Mem: Fix incorrect logic in bus blocksize check	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish