gem5 - gem5

Age	Commit message (Expand)	Author
2013-06-18	ruby: restrict Address to being a type and not a variable name	Lena Olson
2013-06-18	kvm: Use the address finalization code in the TLB	Andreas Sandberg
2013-06-09	ruby: remove several unused variables in Profiler	Nilay Vaish
2013-06-09	ruby: remove periodic event from Profiler	Nilay Vaish
2013-06-09	ruby: stats: use gem5's stats for cache and memory controllers	Nilay Vaish
2013-06-09	ruby: remove undefined functions in Address class	Nilay Vaish
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-05-30	mem: Make returning snoop responses occupy response layer	Andreas Hansson
2013-05-30	mem: Make the buses multi layered	Andreas Hansson
2013-05-30	mem: Separate the two snoop response cases in the bus	Andreas Hansson
2013-05-30	mem: Tidy up a few variables in the bus	Andreas Hansson
2013-05-30	mem: Add basic stats to the buses	Uri Wiener
2013-05-30	mem: Use unordered set in bus request tracking	Andreas Hansson
2013-05-30	mem: Check for waiting state in bus draining	Andreas Hansson
2013-05-30	mem: Add a LPDDR3-1600 configuration	Andreas Hansson
2013-05-30	mem: Adapt the LPDDR2 to match a single x32 channel	Andreas Hansson
2013-05-30	mem: Avoid explicitly zeroing the memory backing store	Andreas Hansson
2013-05-21	ruby: slicc: fix error msg in TypeFieldMemberAST.py	Malek Musleh
2013-05-21	ruby: moesi hammer: cosmetic changes	Nilay Vaish
2013-05-21	ruby: mesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp token: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: add stats to .sm files, remove cache profiler	Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23	sim: Fix two bugs relating to software caching of PageTable entries.	Mitch Hayenga
2013-04-23	ruby: mesi coherence protocol: remove unused state M_MB	Nilay Vaish
2013-04-23	ruby: patch checkpoint restore with garnet	Nilay Vaish
2013-04-22	mem: Address mapping with fine-grained channel interleaving	Andreas Hansson
2013-04-22	mem: More descriptive enum names for address mapping	Andreas Hansson
2013-04-22	mem: Add a WideIO DRAM configuration	Andreas Hansson
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
2013-04-22	mem: Replace check with panic where inhibited should not happen	Andreas Hansson
2013-04-22	sim: separate nextCycle() and clockEdge() in clockedObjects	Dam Sunwoo
2013-04-17	ruby: moesi cmp directory: add copyright notice	Nilay Vaish
2013-04-09	Ruby: Fix RubyPort evict packet memory leak	Joel Hestness
2013-04-09	Ruby: Delete packet requests during warmup	Joel Hestness
2013-04-09	Ruby: Add field to slicc machine for generic type	Joel Hestness
2013-04-09	Ruby: Order profilers based on version	Joel Hestness
2013-04-09	Ruby: More descriptive message buffer connection fatal	Jason Power
2013-04-09	Ruby: Fix typo in Slicc if-statement AST error	Jason Power
2013-04-07	Ruby System, Cache Recorder: Use delete [] for trace vars	Joel Hestness
2013-03-27	mem: Fix cache latency bug	Mitch Hayenga
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-03-26	mem: Separate waiting for the bus and waiting for a peer	Andreas Hansson
2013-03-26	mem: Introduce a variable for the retrying port	Andreas Hansson
2013-03-26	mem: Add optional request flags to the packet trace	Andreas Hansson
2013-03-22	ruby: slicc: set sender, receiver clock objs for optional queue	Nilay Vaish