gem5 - gem5

Age	Commit message (Expand)	Author
2013-03-27	mem: Fix cache latency bug	Mitch Hayenga
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-03-26	mem: Separate waiting for the bus and waiting for a peer	Andreas Hansson
2013-03-26	mem: Introduce a variable for the retrying port	Andreas Hansson
2013-03-26	mem: Add optional request flags to the packet trace	Andreas Hansson
2013-03-22	ruby: slicc: set sender, receiver clock objs for optional queue	Nilay Vaish
2013-03-22	ruby: message buffer: correct previous errors	Nilay Vaish
2013-03-22	ruby: message buffer: remove _ptr from some variables	Nilay Vaish
2013-03-22	ruby: message buffer node: used Tick in place of Cycles	Nilay Vaish
2013-03-22	ruby: consumer: avoid using receiver side clock	Nilay Vaish
2013-03-22	ruby: remove unsued profile functions	Nilay Vaish
2013-03-22	ruby: keep histogram of outstanding requests in seq	Nilay Vaish
2013-03-22	slicc: remove check if the L1Cache has a sequencer	Nilay Vaish
2013-03-22	ruby: move stall and wakeup functions to AbstractController	Nilay Vaish
2013-03-22	ruby: connect two controllers using only message buffers	Nilay Vaish
2013-03-22	ruby: convert Topology to regular class	Nilay Vaish
2013-03-22	ruby: network: move routers from topology to network	Nilay Vaish
2013-03-18	mem: Fix missing delete of packet in DRAM access	Andreas Hansson
2013-03-15	ruby: set: corrects csprintf() call introduced by 7d95b650c9b6	Nilay Vaish
2013-03-07	ruby: Fix gcc 4.8 maybe-uninitialized compilation error	Andreas Hansson
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2013-03-06	ruby: garnet: fixed: implement functional access	Nilay Vaish
2013-03-02	ruby: fixes functional writes to RubyRequest	Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-01	mem: Add check if SimpleDRAM nextReqEvent is scheduled	Andreas Hansson
2013-03-01	mem: Add a method to build multi-channel DRAM configurations	Andreas Hansson
2013-03-01	mem: SimpleDRAM variable naming and whitespace fixes	Andreas Hansson
2013-03-01	mem: Add support for multi-channel DRAM configurations	Andreas Hansson
2013-03-01	mem: Merge interleaved ranges when creating backing store	Andreas Hansson
2013-03-01	mem: Merge ranges in bus before passing them on	Andreas Hansson
2013-02-28	ruby: mesi coherence protocol: invalidate lock	Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-02-19	slicc: remove unused variable message_buffer_names	Nilay Vaish
2013-02-19	ruby: remove unused variable m_print_config in class Topology	Nilay Vaish
2013-02-19	mem: Fix sender state bug and delay popping	Andreas Hansson
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-02-19	mem: Fix SenderState related cache deadlock	Sascha Bischoff
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-19	mem: Ensure trace captures packet fields before forwarding	Andreas Hansson
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-14	Ruby: Fix compilation errors on gcc 4.7 and clang 3.2	Andreas Hansson
2013-02-10	ruby: MI protocol: add a missing transition	Nilay Vaish
2013-02-10	ruby: enable multiple clock domains	Nilay Vaish
2013-02-10	ruby: replace Time with Cycles (final patch in the series)	Nilay Vaish