| Age | Commit message (Expand) | Author |
|---|
| 2007-11-15 | branch merge | Korey Sewell |
| 2007-11-14 | Checkpointing: Name SE page table entries better so that there isn't a proble... | Ali Saidi |
| 2007-11-14 | remove unnecessary debug messages I added | Korey Sewell |
| 2007-11-13 | Add in files from merge-bare-iron, get them compiling in FS and SE mode | Korey Sewell |
| 2007-11-04 | Cache: Fix for OS X 10.5 compiling. | Ali Saidi |
| 2007-11-01 | DRAM: Make latency parameters be Param.Latency instead of ints. | Ali Saidi |
| 2007-10-31 | Merge in bus DPRINTF changes. | Steve Reinhardt |
| 2007-10-31 | Traceflags: Add SCons function to created a traceflag instead of having one f... | Ali Saidi |
| 2007-10-25 | TLB: Fix serialization issues with the tlb entries and make the page table st... | Gabe Black |
| 2007-10-25 | SE: Fix page table and system serialization, don't reinit process if this is ... | Ali Saidi |
| 2007-09-16 | mem: clean up bus/cache DPRINTFs a bit | Steve Reinhardt |
| 2007-09-05 | Bus: Fix drain code; old method could return 1 in atomic mode and never call ... | Ali Saidi |
| 2007-08-30 | params: Deprecate old-style constructors; update most SimObject constructors. | Miles Kaufmann |
| 2007-08-26 | Merge with head | Gabe Black |
| 2007-08-26 | Address translation: Make the page table more flexible. | Gabe Black |
| 2007-08-12 | MemorySystem: Fix the use of ?: to produce correct results. | Ali Saidi |
| 2007-08-10 | DMA: Add IOCache and fix bus bridge to optionally only send requests one | Ali Saidi |
| 2007-08-10 | Bus: Only call end() on an stl object once in a loop | Ali Saidi |
| 2007-08-08 | Port, StaticInst: Revert unnecessary changes. | Vincentius Robby |
| 2007-08-08 | alpha: Make the TLB cache to actually work. | Vincentius Robby |
| 2007-08-04 | port: Implement cache for port interfaces and ranges | Vincentius Robby |
| 2007-08-03 | cache: get rid of obsolete params from python. | Steve Reinhardt |
| 2007-07-29 | memory system: fix functional access bug. | Steve Reinhardt |
| 2007-07-29 | bus: take out response prioritization (timing was messed up). | Steve Reinhardt |
| 2007-07-27 | packet: get rid of unused intersect() function. | Steve Reinhardt |
| 2007-07-27 | cache/memtest: fixes for functional accesses. | Steve Reinhardt |
| 2007-07-27 | cache: Get rid of unused variable. | Steve Reinhardt |
| 2007-07-26 | Merge python and x86 changes with cache branch | Nathan Binkert |
| 2007-07-26 | Have owner respond to UpgradeReq to avoid race. | Steve Reinhardt |
| 2007-07-26 | Add downward express snoops for invalidations. | Steve Reinhardt |
| 2007-07-26 | Continue snooping after a writeback is encountered. | Steve Reinhardt |
| 2007-07-26 | bus: Fix default port handling. | Steve Reinhardt |
| 2007-07-25 | Can't block on memInhibit packets | Steve Reinhardt |
| 2007-07-24 | Integrate snoop loop functions into their respective call sites. | Steve Reinhardt |
| 2007-07-24 | Don't delete request at target... requester still needs it. | Steve Reinhardt |
| 2007-07-23 | A couple more minor bug fixes for multilevel coherence. | Steve Reinhardt |
| 2007-07-23 | Major changes to how SimObjects are created and initialized. Almost all | Nathan Binkert |
| 2007-07-22 | Replace lowerMSHRPending flag with more robust scheme | Steve Reinhardt |
| 2007-07-22 | Replace DeferredSnoop flag with LowerMSHRPending flag. | Steve Reinhardt |
| 2007-07-22 | A few minor non-debug compilation issues. | Steve Reinhardt |
| 2007-07-21 | Deal with invalidations intersecting outstanding upgrades. | Steve Reinhardt |
| 2007-07-21 | Several more fixes for multi-level timing coherence. | Steve Reinhardt |
| 2007-07-17 | Make sure responses never get blocked. | Steve Reinhardt |
| 2007-07-17 | Forward cache-to-cache responses through other caches. | Steve Reinhardt |
| 2007-07-17 | Assert that an mshr has a target in getTarget(). | Steve Reinhardt |
| 2007-07-15 | Fix up a bunch of multilevel coherence issues. | Steve Reinhardt |
| 2007-07-15 | Make Bus::findPort() a little more useful. | Steve Reinhardt |
| 2007-07-14 | Add CacheRepl trace flag and move a couple DPRINTFs to it. | Steve Reinhardt |
| 2007-07-14 | Move a couple of DPRINTFs from Cache to CachePort. | Steve Reinhardt |
| 2007-07-14 | Fix bug in copying packet with static data pointer. | Steve Reinhardt |
