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path: root/src/mem
AgeCommit message (Expand)Author
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
2007-11-28Make ports that aren't connected to anything fail more gracefully.Gabe Black
2007-11-19Memory: Cache the physical memory start and size so we don't need a dynamic c...Ali Saidi
2007-11-16Tweak check for writable block fill.Steve Reinhardt
2007-11-16Fix bug on exclusive response to ReadReq with pending WriteReq.Steve Reinhardt
2007-11-15branch mergeKorey Sewell
2007-11-14Checkpointing: Name SE page table entries better so that there isn't a proble...Ali Saidi
2007-11-14remove unnecessary debug messages I addedKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-11-04Cache: Fix for OS X 10.5 compiling.Ali Saidi
2007-11-01DRAM: Make latency parameters be Param.Latency instead of ints.Ali Saidi
2007-10-31Merge in bus DPRINTF changes.Steve Reinhardt
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-10-25TLB: Fix serialization issues with the tlb entries and make the page table st...Gabe Black
2007-10-25SE: Fix page table and system serialization, don't reinit process if this is ...Ali Saidi
2007-09-16mem: clean up bus/cache DPRINTFs a bitSteve Reinhardt
2007-09-05Bus: Fix drain code; old method could return 1 in atomic mode and never call ...Ali Saidi
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-26Address translation: Make the page table more flexible.Gabe Black
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-10Bus: Only call end() on an stl object once in a loopAli Saidi
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-04port: Implement cache for port interfaces and rangesVincentius Robby
2007-08-03cache: get rid of obsolete params from python.Steve Reinhardt
2007-07-29memory system: fix functional access bug.Steve Reinhardt
2007-07-29bus: take out response prioritization (timing was messed up).Steve Reinhardt
2007-07-27packet: get rid of unused intersect() function.Steve Reinhardt
2007-07-27cache/memtest: fixes for functional accesses.Steve Reinhardt
2007-07-27cache: Get rid of unused variable.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-26Have owner respond to UpgradeReq to avoid race.Steve Reinhardt
2007-07-26Add downward express snoops for invalidations.Steve Reinhardt
2007-07-26Continue snooping after a writeback is encountered.Steve Reinhardt
2007-07-26bus: Fix default port handling.Steve Reinhardt
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