gem5 - gem5

Age	Commit message (Expand)	Author
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-10-31	mem: Fix typo in port comments	Andreas Hansson
2012-10-25	dev: Make default clock more reasonable for system and devices	Andreas Hansson
2012-10-18	ruby: functional access updates to network test protocol	Nilay Vaish
2012-10-15	ruby: improved support for functional accesses	Nilay Vaish
2012-10-15	ruby: register multiple memory controllers	Nilay Vaish
2012-10-15	ruby: remove AbstractMemOrCache	Nilay Vaish
2012-10-15	ruby: allow function definition in slicc structs	Nilay Vaish
2012-10-15	ruby banked array: do away with event scheduling	Nilay Vaish
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Mem: Fix incorrect logic in bus blocksize check	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Mem: Use deque instead of list for bus retries	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-10-15	Mem: Use range operations in bus in preparation for striping	Andreas Hansson
2012-10-11	Mem: Determine bus block size during initialisation	Andreas Hansson
2012-10-02	ruby: makes some members non-static	Nilay Vaish
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-10-02	ruby: rename template_hack to template	Nilay Vaish
2012-10-02	ruby: remove unused code in protocols	Nilay Vaish
2012-10-02	ruby: remove some unused things in slicc	Nilay Vaish
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-30	MI coherence protocol: add copyright notice	Nilay Vaish
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-25	mem: Add a gasket that allows memory ranges to be re-mapped.	Ali Saidi
2012-09-23	RubyPort and Sequencer: Fix draining	Joel Hestness
2012-09-21	DRAM: Introduce SimpleDRAM to capture a high-level controller	Andreas Hansson
2012-09-21	Mem: Tidy up bus member variables types	Andreas Hansson
2012-09-20	bus: removed outdated warn regarding 64 B block sizes	Anthony Gutierrez
2012-09-19	Mem: Remove the file parameter from AbstractMemory	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-18	ruby: eliminate typedef integer_t	Nilay Vaish
2012-09-18	ruby: avoid using g_system_ptr for event scheduling	Nilay Vaish
2012-09-18	Mem: Add a maximum bandwidth to SimpleMemory	Andreas Hansson
2012-09-14	scons: Use c++0x with gcc >= 4.4 instead of 4.6	Andreas Hansson
2012-09-12	Ruby: Modify Scons so that we can put .sm files in extras	Jason Power
2012-09-11	clang: Fix issues identified by the clang static analyzer	Andreas Hansson
2012-09-11	Cache: Split invalidateBlk up to seperate block vs. tags	Lena Olson
2012-09-11	Ruby: Use uint32_t instead of uint32 everywhere	Nilay Vaish
2012-09-11	Ruby: Use uint8_t instead of uint8 everywhere	Nilay Vaish
2012-09-10	Ruby System: Convert to Clocked Object	Nilay Vaish
2012-09-10	Ruby Slicc: remove the call to cin.get() function	Nilay Vaish
2012-09-10	Mem: Allow serializing of more than INT_MAX bytes	Marco Elver
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-09-05	Ruby Memory Controller: Fix clocking	Joel Hestness