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AgeCommit message (Expand)Author
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness
2012-08-28Ruby: Correct DataBlock =operatorJason Power
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Port: Stricter port bind/unbind semanticsAndreas Hansson
2012-08-27Ruby: remove README.debugging and Decommissioning_noteNilay Vaish
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
2012-08-27Ruby Memory Vector: Allow more than 4GB of memoryNilay Vaish
2012-08-25MESI Protocol: Correct the virtual network in profile functionsNilay Vaish
2012-08-25MESI Coherence Protocol: Add copyright noticeNilay Vaish
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-21PacketQueue: Allow queuing in the same tick as desired send tickAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-19Ruby Banked Array: add copyrightsNilay Vaish
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-08-10Ruby: Clean up topology changesJason Power
2012-08-06SETranslatingPortProxy: fix bug in tryReadString()Steve Reinhardt
2012-08-01Ruby NetDest: add assert for bad element in netdestJason Power
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-23Bridge: Use EventWrapper instead of Event subclass for sendEventAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10imported patch jason/slicc-external-structure-fixBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-07-09Mem: Make members relating to range and size constantAndreas Hansson
2012-07-09Port: Hide the queue implementation in SimpleTimingPortAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add getAddrRanges to master port (asking slave port)Andreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo