gem5 - gem5

Age	Commit message (Expand)	Author
2012-06-29	Mem: Fix a livelock resulting in LLSC/locked memory access implementation.	Matt Evans
2012-06-29	Cache: Only invalidate a line in the cache when an uncacheable write is seen.	Ali Saidi
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-06-05	Mem: add per-master stats to physmem	Dam Sunwoo
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-30	Bus: Remove redundant packet parameter from isOccupied	Andreas Hansson
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-30	Packet: Updated comments for src and dest fields	Andreas Hansson
2012-05-30	Bridge: Split deferred request, response and sender state	Andreas Hansson
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-23	Packet: Cleaning up packet command and attribute	Andreas Hansson
2012-05-22	Ruby: Remove the unused src/mem/ruby/common/Driver.* files.	Nilay Vaish
2012-05-22	Ruby Sequencer: Schedule deadlock check event at correct time	Nilay Vaish
2012-05-10	mem: fix bug with CopyStringOut and null string termination.	Ali Saidi
2012-05-10	Cache: restructure code that actually isn't a loop	Ali Saidi
2012-05-10	gem5: assert before indexing intro arrays to verify bounds	Ali Saidi
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-09	MEM: Add the communication monitor	Andreas Hansson
2012-05-08	MEM: Do not forward uncacheable to bus snoopers	Andreas Hansson
2012-05-04	Ruby: Ensure snoop requests are sent using sendTimingSnoopReq	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-28	Garnet: Correct computation of link utilization	Nilay Vaish
2012-04-25	Ruby: Remove extra statements from Sequencer	Nilay Vaish
2012-04-25	MEM: Use base class Master/SlavePort pointers in the bus	Andreas Hansson
2012-04-25	MEM: Add the PortId type and a corresponding id field to Port	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-14	clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6	Andreas Hansson
2012-04-12	Ruby: Ensure order-dependent iteration uses an ordered map	Andreas Hansson
2012-04-06	slicc: Controllers attached to Sequencers no longer have to be named L1Cache.	Lisa Hsu
2012-04-06	sim-ruby: checkpointing fixes and dependent eventq improvements	Brad Beckmann
2012-04-06	slicc: fixed error message when the type has no inheritance	Brad Beckmann
2012-04-06	MOESI_hammer: tbe allocation and dependent wakeup fixes	Brad Beckmann
2012-04-06	MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...	Brad Beckmann
2012-04-06	rubytest: seperated read and write ports.	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Remove legacy DRAM in preparation for memory updates	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-23	Ruby: Fix Set::print for 32-bit hosts	Andreas Hansson
2012-03-22	MEM: Unify bus access methods and prepare for master/slave split	Andreas Hansson
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-22	Scons: Remove Werror=False in SConscript files	Andreas Hansson
2012-03-19	Garnet: Stats at vnet granularity + code cleanup	Tushar Krishna
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-06	build scripts: Made minor modifications to reduce build overhead time.	Marc Orr