index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem
Age
Commit message (
Expand
)
Author
2007-06-05
Clean up some of vincent's code and commit it
Ali Saidi
2007-05-30
tport.cc:
Steve Reinhardt
2007-05-29
A little more cleanup & refactoring of SimpleTimingPort.
Steve Reinhardt
2007-05-28
Restructure SimpleTimingPort a bit:
Steve Reinhardt
2007-05-28
Reformat comments to meet line length restriction.
Steve Reinhardt
2007-05-27
Move SimObject python files alongside the C++ and fix
Nathan Binkert
2007-05-21
Change getDeviceAddressRanges to use bool for snoop arg.
Steve Reinhardt
2007-05-20
Insist that PhysicalMemory object have at least one connection.
Steve Reinhardt
2007-05-19
Oops... some places in C++ explicitly ask for a "functional"
Steve Reinhardt
2007-05-19
PhysicalMemory has vector of uniform ports instead of one special one.
Steve Reinhardt
2007-05-15
Merge zizzer:/bk/newmem
Ali Saidi
2007-05-15
hopefully the final hacky change to make the bus bridge work ok
Ali Saidi
2007-05-14
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-05-14
add uglyiness to fix dmas
Ali Saidi
2007-05-13
Eliminate unused PacketPtr from BaseCache's
Steve Reinhardt
2007-05-13
Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.
Steve Reinhardt
2007-05-13
fix handling of atomic packets
Ali Saidi
2007-05-10
remove hit_latency and make latency do the right thing
Ali Saidi
2007-05-09
undo my previous bus change, it can make the bus deadlock.. so it still const...
Ali Saidi
2007-05-09
add a backoff algorithm when nacks are received by devices
Ali Saidi
2007-05-09
fix the translating ports so it can add a page on a fault
Ali Saidi
2007-05-07
the bridge never returns false when recvTiming() is called on its ports now, ...
Ali Saidi
2007-05-07
fix partial writes with a functional memory hack
Ali Saidi
2007-04-04
The MemoryObject tha owns a port should delete it if it so chooses when delet...
Ali Saidi
2007-03-28
Call compare and Swap on the target, not the response.
Ron Dreslinski
2007-03-27
Merge zizzer:/bk/newmem
Ron Dreslinski
2007-03-27
First Pass At Cmp/Swap in caches
Ron Dreslinski
2007-03-23
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2007-03-23
3 memory system fixes:
Kevin Lim
2007-03-12
Clean up more memory leaks
Ron Dreslinski
2007-03-12
Fix some of the memory leaks related to writebacks
Ron Dreslinski
2007-03-10
Rework the way SCons recurses into subdirectories, making it
Nathan Binkert
2007-03-09
Two fixes:
Kevin Lim
2007-03-08
stop m5 from leaking like a sieve
Ali Saidi
2007-03-07
Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same ...
Gabe Black
2007-03-07
Make byteswap work correctly on Twin??_t types.
Gabe Black
2007-03-06
Move all of the parameters of the Root SimObject so they are
Nathan Binkert
2007-03-02
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...
Ali Saidi
2007-02-18
implement vtophys and 32bit gdb support
Ali Saidi
2007-02-12
some forgotten commits
Ali Saidi
2007-02-12
rename store conditional stuff as extra data so it can be used for conditiona...
Ali Saidi
2007-02-07
Merge zizzer.eecs.umich.edu:/bk/newmem
Steve Reinhardt
2007-02-07
Make memory commands dense again to avoid cache stat table explosion.
Steve Reinhardt
2007-02-06
More DPRINTF cleanup.
Steve Reinhardt
2007-02-06
Include compiler.hh since we use some of the #defines
Nathan Binkert
2007-02-06
Minor DPRINTF fixes.
Steve Reinhardt
2007-02-06
Fix for LL/SC that Ron sent me.
Kevin Lim
2007-01-27
While I'm waiting for legion to run make m5 compile with a few more compilers
Ali Saidi
2007-01-26
make our code a little more standards compliant
Ali Saidi
2006-12-27
Merge zizzer:/bk/newmem
Ali Saidi
[next]