summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-10-31mem: Fix typo in port commentsAndreas Hansson
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15 ruby: register multiple memory controllersNilay Vaish
2012-10-15ruby: remove AbstractMemOrCacheNilay Vaish
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Mem: Fix incorrect logic in bus blocksize checkAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-10-02ruby: remove some unused things in sliccNilay Vaish
2012-10-02ruby: move functional access to ruby systemNilay Vaish
2012-09-30MI coherence protocol: add copyright noticeNilay Vaish
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-25mem: Add a gasket that allows memory ranges to be re-mapped.Ali Saidi
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-20bus: removed outdated warn regarding 64 B block sizesAnthony Gutierrez
2012-09-19Mem: Remove the file parameter from AbstractMemoryAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
2012-09-18Mem: Add a maximum bandwidth to SimpleMemoryAndreas Hansson
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
2012-09-10Mem: Allow serializing of more than INT_MAX bytesMarco Elver
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness