gem5 - gem5

Age	Commit message (Expand)	Author
2013-05-30	mem: Adapt the LPDDR2 to match a single x32 channel	Andreas Hansson
2013-05-30	mem: Avoid explicitly zeroing the memory backing store	Andreas Hansson
2013-05-21	ruby: slicc: fix error msg in TypeFieldMemberAST.py	Malek Musleh
2013-05-21	ruby: moesi hammer: cosmetic changes	Nilay Vaish
2013-05-21	ruby: mesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp token: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: add stats to .sm files, remove cache profiler	Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23	sim: Fix two bugs relating to software caching of PageTable entries.	Mitch Hayenga
2013-04-23	ruby: mesi coherence protocol: remove unused state M_MB	Nilay Vaish
2013-04-23	ruby: patch checkpoint restore with garnet	Nilay Vaish
2013-04-22	mem: Address mapping with fine-grained channel interleaving	Andreas Hansson
2013-04-22	mem: More descriptive enum names for address mapping	Andreas Hansson
2013-04-22	mem: Add a WideIO DRAM configuration	Andreas Hansson
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
2013-04-22	mem: Replace check with panic where inhibited should not happen	Andreas Hansson
2013-04-22	sim: separate nextCycle() and clockEdge() in clockedObjects	Dam Sunwoo
2013-04-17	ruby: moesi cmp directory: add copyright notice	Nilay Vaish
2013-04-09	Ruby: Fix RubyPort evict packet memory leak	Joel Hestness
2013-04-09	Ruby: Delete packet requests during warmup	Joel Hestness
2013-04-09	Ruby: Add field to slicc machine for generic type	Joel Hestness
2013-04-09	Ruby: Order profilers based on version	Joel Hestness
2013-04-09	Ruby: More descriptive message buffer connection fatal	Jason Power
2013-04-09	Ruby: Fix typo in Slicc if-statement AST error	Jason Power
2013-04-07	Ruby System, Cache Recorder: Use delete [] for trace vars	Joel Hestness
2013-03-27	mem: Fix cache latency bug	Mitch Hayenga
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-03-26	mem: Separate waiting for the bus and waiting for a peer	Andreas Hansson
2013-03-26	mem: Introduce a variable for the retrying port	Andreas Hansson
2013-03-26	mem: Add optional request flags to the packet trace	Andreas Hansson
2013-03-22	ruby: slicc: set sender, receiver clock objs for optional queue	Nilay Vaish
2013-03-22	ruby: message buffer: correct previous errors	Nilay Vaish
2013-03-22	ruby: message buffer: remove _ptr from some variables	Nilay Vaish
2013-03-22	ruby: message buffer node: used Tick in place of Cycles	Nilay Vaish
2013-03-22	ruby: consumer: avoid using receiver side clock	Nilay Vaish
2013-03-22	ruby: remove unsued profile functions	Nilay Vaish
2013-03-22	ruby: keep histogram of outstanding requests in seq	Nilay Vaish
2013-03-22	slicc: remove check if the L1Cache has a sequencer	Nilay Vaish
2013-03-22	ruby: move stall and wakeup functions to AbstractController	Nilay Vaish
2013-03-22	ruby: connect two controllers using only message buffers	Nilay Vaish
2013-03-22	ruby: convert Topology to regular class	Nilay Vaish
2013-03-22	ruby: network: move routers from topology to network	Nilay Vaish
2013-03-18	mem: Fix missing delete of packet in DRAM access	Andreas Hansson
2013-03-15	ruby: set: corrects csprintf() call introduced by 7d95b650c9b6	Nilay Vaish
2013-03-07	ruby: Fix gcc 4.8 maybe-uninitialized compilation error	Andreas Hansson
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2013-03-06	ruby: garnet: fixed: implement functional access	Nilay Vaish
2013-03-02	ruby: fixes functional writes to RubyRequest	Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-01	mem: Add check if SimpleDRAM nextReqEvent is scheduled	Andreas Hansson
2013-03-01	mem: Add a method to build multi-channel DRAM configurations	Andreas Hansson