gem5 - gem5

Age	Commit message (Expand)	Author
2014-07-25	mem: Add missig timing and current parameters to DRAM configs	Omar Naji
2014-10-09	mem: Remove DRAMSim2 DDR3 configuration	Omar Naji
2014-10-09	mem: Add packet sanity checks to cache and MSHRs	Andreas Hansson
2014-10-09	mem: Allow packet queue to move next send event forward	Andreas Hansson
2014-10-01	misc: Fix issues identified by static analysis	Andreas Hansson
2014-09-27	mem: Output precise range when XBar has conflicts	Curtis Dunham
2014-09-27	mem: Provide better diagnostic for unconnected port	Curtis Dunham
2014-09-27	misc: Fix a bunch of minor issues identified by static analysis	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-04-25	mem: Add access statistics for the snoop filter	Stephan Diestelhorst
2014-09-20	mem: Tie in the snoop filter in the coherent bus	Stephan Diestelhorst
2014-04-24	mem: Add a simple snoop counter per bus	Stephan Diestelhorst
2014-09-20	mem: Simple Snoop Filter	Stephan Diestelhorst
2014-09-20	mem: Add DDR4 bank group timing	Wendy Elsasser
2014-09-20	mem: Add memory rank-to-rank delay	Wendy Elsasser
2014-09-20	mem: Remove the GHB prefetcher from the source tree	Mitch Hayenga
2014-09-19	misc: Use safe_cast when assumptions are made about return value	Andreas Hansson
2014-09-19	misc: Remove assertions ensuring unsigned values >= 0	Andreas Hansson
2014-09-19	mem: Check return value of checkFunctional in SimpleMemory	Andreas Hansson
2014-09-19	mem: Add checks to sendTimingReq in cache	Andreas Hansson
2014-09-15	ruby: network: revert some of the changes from ad9c042dce54	Nilay Vaish
2014-09-09	mem: Add accessor function for vaddr	Mitch Hayenga
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-09-03	base: Use the global Mersenne twister throughout	Andreas Hansson
2014-09-03	mem: Avoid unecessary retries when bus peer is not ready	Andreas Hansson
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-09-03	mem: Fix a bug in the cache port flow control	Andreas Hansson
2014-05-13	cpu, mem: Make software prefetches non-blocking	Curtis Dunham
2014-05-13	mem: Refactor assignment of Packet types	Curtis Dunham
2014-09-03	cache: Fix handling of LL/SC requests under contention	Geoffrey Blake
2014-09-03	mem: Packet queue clean up	Andreas Hansson
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-09-01	ruby: remove typedef of Index as int64	Nilay Vaish
2014-09-01	ruby: PerfectSwitch: moves code to a per vnet helper function	Nilay Vaish
2014-09-01	ruby: message buffers: significant changes	Nilay Vaish
2014-09-01	build opts: add MI_example to NULL ISA	Nilay Vaish
2014-09-01	mem: change the namespace Message to ProtoMessage	Nilay Vaish
2014-09-01	ruby: slicc: change the way configurable members are specified	Nilay Vaish
2014-09-01	ruby: slicc: improve the grammar	Nilay Vaish
2014-09-01	ruby: mesi three level: slight naming changes.	Nilay Vaish
2014-09-01	ruby: slicc: donot prefix machine name to variables	Nilay Vaish
2014-09-01	ruby: remove unused toString() from AbstractController	Nilay Vaish
2014-09-01	ruby: network: move getNumNodes() to base class	Nilay Vaish
2014-09-01	ruby: eliminate type Time	Nilay Vaish
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish
2014-08-28	mem: adding architectural page table support for SE mode	Alexandru
2014-04-01	mem: adding a multi-level page table class	Alexandru
2014-08-26	mem: Fix DRAMSim2 cycle check when restoring from checkpoint	Andreas Hansson
2014-08-26	mem: Update DRAM controller comments	Andreas Hansson
2014-08-26	mem: Fix address interleaving bug in DRAM controller	Andreas Hansson