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path: root/src/mem
AgeCommit message (Expand)Author
2015-03-27mem: Ignore uncacheable MSHRs when finding matchesAndreas Hansson
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
2015-03-27mem: Modernise MSHR iterators to C++11Andreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
2015-03-27mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHEDAli Jafri
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-03-23mem: Tidy up RequestAndreas Hansson
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2015-03-19mem: Enable CommMonitor to output traces in atomic modeGeoffrey Blake
2015-02-11mem: remove redundant test in in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: add local var in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-14mem: clean up write buffer check in Cache::handleSnoop()Steve Reinhardt
2015-03-02mem: Unify all cache DPRINTF address formattingAndreas Hansson
2015-03-02mem: Fix cache MSHR conflict determinationAndreas Hansson
2015-03-02mem: Add byte mask to Packet::checkFunctionalAndreas Hansson
2015-03-02mem: Add option to force in-order insertion in PacketQueueStephan Diestelhorst
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02mem: Add crossbar latenciesMarco Balboni
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2015-01-22mem: Remove unused Packet src and dest fieldsAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-22mem: Remove unused RequestState in the bridgeAndreas Hansson
2015-01-22mem: Always use SenderState for response routing in RubyPortAndreas Hansson
2015-01-22mem: Make the XBar responsible for tracking response routingAndreas Hansson
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Fix event scheduling issue for prefetchesMitch Hayenga
2014-12-23mem: Fix bug relating to writebacks and prefetchesMitch Hayenga
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-12-23mem: Fix a bug in the DRAM controller arbitrationOmar Naji
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 18:32:37 +0000