Age | Commit message (Collapse) | Author |
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--HG--
extra : convert_revision : 76377ca2e4d7ea70d1d54d325a63ce710e260b93
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extra : convert_revision : 370f9e34911157765be6fd49e826fa1af589b466
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based on following Packet senderState links.
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extra : convert_revision : 9027d59bd7242aa0e4275bf94d8b1fb27bd59d79
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Turns out DeferredSnoop isn't quite the right bit of info
we needed... see new comment in cache_impl.hh.
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extra : convert_revision : a38de8c1677a37acafb743b7074ef88b21d3b7be
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extra : convert_revision : d59a5cad6187a2229dddd1a48282ebd2923d1d8d
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If the invalidation beats the upgrade at a lower level
then the upgrade must be converted to a read exclusive
"in the field".
Restructure target list & deferred target list to
factor out some common code.
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extra : convert_revision : 7bab4482dd6c48efdb619610f0d3778c60ff777a
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- Add "deferred snoop" flag to Packet so upper-level caches
can distinguish whether lower-level cache request was
in-service or not at the time of the original snoop.
- Revamp response handling to properly handle deferred snoops
on non-cache-fill requests (i.e. upgrades).
- Make sure forwarded writebacks are kept in write buffer at
lower-level caches so they get snooped properly.
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extra : convert_revision : 17f8a3772a1ae31a16991a53f8225ddf54d31fc9
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extra : convert_revision : 29f359d743994a94dc403aa0621ba72cd137d1a1
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--HG--
extra : convert_revision : 5b6a02255bccd98b00949703cf4ba4b221553cea
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extra : convert_revision : 08091670fc319876012ed139fcd2584c364a980c
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Atomic mode seems to work. Timing is closer but not there yet.
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extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
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Move check for loops outside, since half the call sites
end up working around it anyway. Return integer port ID
instead of port object pointer.
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extra : convert_revision : 4c31fe9930f4d1aa4919e764efb7c50d43792ea3
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extra : convert_revision : 31724d19ebdf2cdc2a2bafff83d17845b3a0b183
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--HG--
extra : convert_revision : 55a0d26660aeb8f63b41897d53e6b2d1f0a163be
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extra : convert_revision : 2fcf99f050d73e007433c1db2475f2893c5961a0
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extra : convert_revision : f99a33b2df6a6c5592856d17d00e73ee83267442
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Note that we should *not* print pointer values in DPRINTFs as
these needlessly clutter tracediff output.
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extra : convert_revision : 25a448f1b3ac8d453a717a104ad6dc0112fb30bb
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extra : convert_revision : b8894d26e1ca7a6c9b736500accdaa53bfb09558
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src/cpu/simple/timing.cc:
Fix another SC problem.
src/mem/cache/cache_impl.hh:
Forgot to call makeTimingResponse() on uncached timing responses.
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extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
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src/cpu/simple/timing.cc:
Fix swap/stq_c command bug.
src/mem/packet.cc:
Fix incorrect LoadLockedReq command response field.
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extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
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Fix atomic timing issue.
src/mem/bus.cc:
Fix atomic timing issue.
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extra : convert_revision : a22ff80cd75f83c785b0604c2a4fde2e2e9f71ef
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extra : convert_revision : af29fc7d0c134f5e89dd2e814c819151350fcb38
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extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
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Handled by Packet::checkFunctional() now.
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extra : convert_revision : 63642254e2789c80a369ac269f317ec054ffe3c0
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(they function as adjectives not nouns)
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extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
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extra : convert_revision : 626255a91679d534030c91bcdb4fc1bed36ceb9b
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Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
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extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
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now encoded in cmd field.
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extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
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extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
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extra : convert_revision : 9bc09d8ae6d50e6dfbb4ab21514612f9aa102a2e
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extra : convert_revision : 703da6128832eb0d5cfed7724e5105f4b3fe4f90
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Change target overflow from assertion to warning.
src/mem/cache/cache_impl.hh:
Change target overflow from assertion to warning.
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extra : convert_revision : ceca990ed916bbf96dedd4836c40df522803f173
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src/mem/cache/tags/lru.cc:
Add some replacement DPRINTFs
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extra : convert_revision : 7993ec24d6af7e7774d04ce36f20e3f43f887fd9
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src/mem/cache/cache_impl.hh:
Handle grants with no packet.
src/mem/cache/miss/mshr.cc:
Fix MSHR snoop hit handling.
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extra : convert_revision : f365283afddaa07cb9e050b2981ad6a898c14451
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sure we don't re-request bus prematurely. Use callback to
avoid calling sendRetry() recursively within recvTiming.
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extra : convert_revision : a907a2781b4b00aa8eb1ea7147afc81d6b424140
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extra : convert_revision : 0fbc28c32c1eeb3dd672df14c1d53bd516f81d0f
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src/cpu/memtest/memtest.cc:
Need to set packet source field so that response from cache
doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
Copy source field when copying packets.
Assert that source is valid before copying it to dest
when turning packets around.
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extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
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Single-cpu timing mode seems to work now.
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extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
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configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.
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extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
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don't spend so much time calling malloc()
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extra : convert_revision : a946564eee46ed7d2aed41c32d488ca7f036c32f
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extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc
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Caused slowdown in performance instead of speeding up.
src/cpu/base.cc:
Removed "adding instead of dividing" trick.
src/mem/bus.cc:
Fixed spelling in comments.
Removed "adding instead of dividing" trick.
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extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
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supposed to and make sure parameters have the right type.
Also make sure that any object that should be an intermediate
type has the right options set.
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extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
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into vm1.(none):/home/stever/bk/newmem-cache2
configs/example/memtest.py:
Hand merge redundant changes.
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extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
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timing mode still broken.
configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
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using a divide in order to not loop forever after resuming from a checkpoint
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extra : convert_revision : 4bbc70b1be4e5c4ed99d4f88418ab620d5ce475a
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--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
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Makes page table cache scheme actually work
src/mem/page_table.cc:
src/mem/page_table.hh:
fix caching scheme to actually work and improve performance
--HG--
extra : convert_revision : 443a8d8acbee540b26affcfdfbf107b8e735d1bd
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into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision : 26921dad179699b7868768361143aaa8d790b8fc
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