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path: root/src/mem
AgeCommit message (Expand)Author
2014-11-14mem: Clarify unit of DRAM controller buffer sizeAndreas Hansson
2014-11-12mem: Delete unused variable in Garnet NetworkLinkMitch Hayenga
2014-11-06ruby: provide a backing storeNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: remove the function functionalReadBuffers()Nilay Vaish
2014-11-06ruby: coherence protocols: remove data block from dirctory entryNilay Vaish
2014-11-06ruby: slicc: allow adding a bool to an int, like C++.Nilay Vaish
2014-11-06ruby: remove sparse memory.Nilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-11-06ruby: dma sequencer: remove RubyPort as parent classNilay Vaish
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-21mem: don't inhibit WriteInv's or defer snoops on their MSHRsCurtis Dunham
2014-10-29mem: have WriteInvalidate obsolete MSHRsCurtis Dunham
2014-10-20mem: Fix DRAM activationlLimit bugOmar Naji
2014-10-20mem: Add DRAM device size and check against configOmar Naji
2014-10-16mem: Modernise PhysicalMemory with C++11 featuresAndreas Hansson
2014-10-16misc: Move AddrRangeList from port.hh to addr_range.hhAndreas Hansson
2014-10-16mem: Add ExternalMaster and ExternalSlave portsAndrew Bardsley
2014-10-16mem: Use shared_ptr for Ruby Message classesAndreas Hansson
2014-10-16arch,x86,mem: Dynamically determine the ISA for Ruby store checkAndreas Hansson
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
2014-10-11ruby: network: garnet: add statistics for different activitiesNilay Vaish
2014-10-11ruby: network: garnet: remove functions for computing powerNilay Vaish
2014-10-11ruby: drop Orion network power modelNilay Vaish
2014-10-11ruby: mesi: slight renamingNilay Vaish
2014-10-11ruby: structures: coorect #ifndef macros in header filesNilay Vaish
2014-07-29mem: DRAMPower integration for on-line DRAM power statsOmar Naji
2014-07-29mem: Add DRAMPower wrapping classOmar Naji
2014-07-25mem: Add missig timing and current parameters to DRAM configsOmar Naji
2014-10-09mem: Remove DRAMSim2 DDR3 configurationOmar Naji
2014-10-09mem: Add packet sanity checks to cache and MSHRsAndreas Hansson
2014-10-09mem: Allow packet queue to move next send event forwardAndreas Hansson
2014-10-01misc: Fix issues identified by static analysisAndreas Hansson
2014-09-27mem: Output precise range when XBar has conflictsCurtis Dunham
2014-09-27mem: Provide better diagnostic for unconnected portCurtis Dunham
2014-09-27misc: Fix a bunch of minor issues identified by static analysisAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-04-25mem: Add access statistics for the snoop filterStephan Diestelhorst
2014-09-20mem: Tie in the snoop filter in the coherent busStephan Diestelhorst
2014-04-24mem: Add a simple snoop counter per busStephan Diestelhorst
2014-09-20mem: Simple Snoop FilterStephan Diestelhorst
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-09-20mem: Remove the GHB prefetcher from the source treeMitch Hayenga
2014-09-19misc: Use safe_cast when assumptions are made about return valueAndreas Hansson
2014-09-19misc: Remove assertions ensuring unsigned values >= 0Andreas Hansson
2014-09-19mem: Check return value of checkFunctional in SimpleMemoryAndreas Hansson
2014-09-19mem: Add checks to sendTimingReq in cacheAndreas Hansson
2014-09-15ruby: network: revert some of the changes from ad9c042dce54Nilay Vaish
2014-09-09mem: Add accessor function for vaddrMitch Hayenga