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path: root/src/mem
AgeCommit message (Expand)Author
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
2013-09-18mem: Fix scheduling bug in SimpleMemoryAndreas Hansson
2013-09-11ruby: Fix Topology throttle connectionsJoel Hestness
2013-09-11ruby: Statically allocate stats in SimpleNetwork, Switch, ThrottleJoel Hestness
2013-09-06ruby: network: convert to gem5 style statsNilay Vaish
2013-09-06ruby: profiler: removes function resourceUsage()Nilay Vaish
2013-09-06ruby: remove undefined message size typeNilay Vaish
2013-09-06ruby: network: removes reset functionalityNilay Vaish
2013-09-06ruby: network: shorten variable namesNilay Vaish
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-08-19stats: Cumulative stats updateAndreas Hansson
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-08-19mem: Warn instead of panic for tXAW violationAndreas Hansson
2013-08-19mem: Allow disabling of tXAW through a 0 activation limitAndreas Hansson
2013-08-19mem: Add an internal packet queue in SimpleMemoryAndreas Hansson
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-07-11ruby: removed the very old double trigger hackBrad Beckmann
2013-06-28ruby: append transition comment only when in opt/debugNilay Vaish
2013-06-28ruby: network: remove reconfiguration codeNilay Vaish
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-06-27mem: Tidy up the bridge with const and additional checksAndreas Hansson
2013-06-27mem: Fix CommMonitor style and response checkAndreas Hansson
2013-06-27mem: Align cache timing to clock edgesAndreas Hansson
2013-06-27mem: Cycles converted to Ticks in atomic cache accessesAndreas Hansson
2013-06-27mem: Remove a redundant heap allocation for a snoop packetAndreas Hansson
2013-06-27mem: Remove CoherentBus snoop port unused private memberAndreas Hansson
2013-06-25ruby: moesi cmp directory: separate actions for external hitsNilay Vaish
2013-06-25ruby: mesi cmp directory: separate actions for external hitsNilay Vaish
2013-06-25ruby: profiler: lots of inter-related changesNilay Vaish