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2011-02-08MESI CMP: Unset TBE pointer in L2 cache controllerNilay Vaish
The TBE pointer in the MESI CMP implementation was not being set to NULL when the TBE is deallocated. This resulted in segmentation fault on testing the protocol when the ProtocolTrace was switched on.
2011-02-07Orion: Replace printf() with fatal()Nilay Vaish
The code for Orion 2.0 makes use of printf() at several places where there as an error in configuration of the model. These have been replaced with fatal().
2011-02-07ruby: add stdio header in SRAM.hhKorey Sewell
missing header file caused RUBY_FS to not compile
2011-02-06ruby: support to stallAndWait the mandatory queueBrad Beckmann
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06ruby: minor fix to deadlock panic messageBrad Beckmann
2011-02-06garnet: Split network power in ruby.statsJoel Hestness
Split out dynamic and static power numbers for printing to ruby.stats
2011-02-06MOESI_hammer: fixed dir bug counting received acksBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06MOESI_CMP_token: removed unused message fieldsTushar Krishna
2011-02-06mem: Added support for Null data packetBrad Beckmann
The packet now identifies whether static or dynamic data has been allocated and is used by Ruby to determine whehter to copy the data pointer into the ruby request. Subsequently, Ruby can be told not to update phys memory when receiving packets.
2011-02-06ruby: Fix RubyPort to properly handle retrysBrad Beckmann
2011-02-06Ruby: Fix to return cache block size to CPU for split data transfersJoel Hestness
2011-02-06Ruby: Add support for locked memory accesses in X86_FSJoel Hestness
2011-02-06Ruby: Update the Ruby request type names for LL/SCJoel Hestness
2011-02-06ruby: Assert for x86 misaligned accessBrad Beckmann
This patch ensures only aligned access are passed to ruby and includes a fix to the DPRINTF address print.
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-06MOESI_hammer: trigge queue fix.Joel Hestness
2011-02-06garnet: added orion2.0 for network power calculationTushar Krishna
2011-02-06garnet: separate data and ctrl VCsTushar Krishna
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC, while data VCs have > 1 buffers per VC. This is for correct power estimations.
2011-01-17Change interface between coherence protocols and CacheMemoryNilay Vaish
The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface.
2011-01-13Ruby: Fixes MESI CMP directory protocolNilay Vaish
The current implementation of MESI CMP directory protocol is broken. This patch, from Arkaprava Basu, fixes the protocol.
2011-01-10ruby: get rid of ruby's Debug.hhNathan Binkert
Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2011-01-04Ruby: Updates MOESI Hammer protocolNilay Vaish
This patch changes the manner in which data is copied from L1 to L2 cache in the implementation of the Hammer's cache coherence protocol. Earlier, data was copied directly from one cache entry to another. This has been broken in to two parts. First, the data is copied from the source cache entry to a transaction buffer entry. Then, data is copied from the transaction buffer entry to the destination cache entry. This has been done to maintain the invariant - at any given instant, multiple caches under a controller are exclusive with respect to each other.
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-12-23PerfectCacheMemory: Add return statements to two functions.Nilay Vaish
Two functions in src/mem/ruby/system/PerfectCacheMemory.hh, tryCacheAccess() and cacheProbe(), end with calls to panic(). Both of these functions have return type other than void. Any file that includes this header file fails to compile because of the missing return statement. This patch adds dummy values so as to avoid the compiler warnings.
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh ↵Nilay Vaish
file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
2010-12-08ruby: remove Ruby asserts for m5.fastBrad Beckmann
This diff is for changing the way ASSERT is handled in Ruby. m5.fast compiles out the assert statements by using the macro NDEBUG. Ruby uses the macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has been put in its place.
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls.
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style.
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08Mem: Finish half-baked support for mmaping file in physmem.Ali Saidi
Physmem has a parameter to be able to mem map a file, however it isn't actually used. This changeset utilizes the parameter so a file can be mmapped.
2010-10-18cache: minor SC assertion fixSteve Reinhardt
Thanks to Joe Gross for finding/testing this.
2010-10-16Mem: Reclaim some request flags used by MIPS for alignment checking.Gabe Black
These flags were being used to identify what alignment a request needed, but the same information is available using the request size. This change also eliminates the isMisaligned function. If more complicated alignment checks are needed, they can be signaled using the ASI_BITS space in the flags vector like is currently done with ARM.
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-09-30CPU/Cache: Fix some errors exposed by valgrindAli Saidi
2010-09-21cache: improve coherence handling of writebacksSteve Reinhardt
If we write back an exclusive copy, we now mark it as such, so the cache receiving the writeback can mark its copy as exclusive. This avoids some unnecessary upgrade requests when a cache later tries to re-acquire exclusive access to the block.
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-09-09code_formatter: make it easier to insert whitespaceNathan Binkert
a newline by just doing "code()". indent() and dedent() now take a "count" parameter to indent/dedent multiple levels.
2010-09-09cache: fail SC when invalidated while waiting for busSteve Reinhardt
Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too.
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt
We can't just obliviously return the first valid cache block we find any more... see comments for details.
2010-09-09cache: coherence protocol enhancements & bug fixesSteve Reinhardt
Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes.
2010-08-26mem: fix m5.fast compile bug in previous csetSteve Reinhardt
2010-08-25cache: fix a bug in atomic multilevel snoopsSteve Reinhardt
2010-08-25mem: fix dumb typo in copyrightsSteve Reinhardt
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24MOESI_hammer: fixed bug for dma reads in single cpu systemsBrad Beckmann
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches ↵Gene Wu
when it in received