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path: root/src/mem
AgeCommit message (Expand)Author
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-23Bridge: Use EventWrapper instead of Event subclass for sendEventAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10imported patch jason/slicc-external-structure-fixBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-07-09Mem: Make members relating to range and size constantAndreas Hansson
2012-07-09Port: Hide the queue implementation in SimpleTimingPortAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Make the default bus width 8 bytes instead of 64Andreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add getAddrRanges to master port (asking slave port)Andreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Bus: enable non/coherent buses sub-classesUri Wiener
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Mem: Fix a livelock resulting in LLSC/locked memory access implementation.Matt Evans
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-05Mem: add per-master stats to physmemDam Sunwoo
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-30Bus: Remove redundant packet parameter from isOccupiedAndreas Hansson
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-30Packet: Updated comments for src and dest fieldsAndreas Hansson
2012-05-30Bridge: Split deferred request, response and sender stateAndreas Hansson
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-23Packet: Cleaning up packet command and attributeAndreas Hansson
2012-05-22Ruby: Remove the unused src/mem/ruby/common/Driver.* files.Nilay Vaish
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
2012-05-10mem: fix bug with CopyStringOut and null string termination.Ali Saidi
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10gem5: assert before indexing intro arrays to verify boundsAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi