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AgeCommit message (Expand)Author
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-06-09Add a startup function that will fast forward to the right clock edgeNathan Binkert
2007-06-09More realistic parametersNathan Binkert
2007-06-05Clean up some of vincent's code and commit itAli Saidi
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-30tport.cc:Steve Reinhardt
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-29A little more cleanup & refactoring of SimpleTimingPort.Steve Reinhardt
2007-05-28Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-28Restructure SimpleTimingPort a bit:Steve Reinhardt
2007-05-28Reformat comments to meet line length restriction.Steve Reinhardt
2007-05-27Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-20Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-15Merge zizzer:/bk/newmemAli Saidi
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-14add uglyiness to fix dmasAli Saidi
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still const...Ali Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-05-09fix the translating ports so it can add a page on a faultAli Saidi
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2007-04-04The MemoryObject tha owns a port should delete it if it so chooses when delet...Ali Saidi
2007-03-28Call compare and Swap on the target, not the response.Ron Dreslinski
2007-03-27Merge zizzer:/bk/newmemRon Dreslinski
2007-03-27First Pass At Cmp/Swap in cachesRon Dreslinski
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-233 memory system fixes:Kevin Lim
2007-03-12Clean up more memory leaksRon Dreslinski
2007-03-12Fix some of the memory leaks related to writebacksRon Dreslinski
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
2007-03-09Two fixes:Kevin Lim
2007-03-08stop m5 from leaking like a sieveAli Saidi
2007-03-07Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same ...Gabe Black
2007-03-07Make byteswap work correctly on Twin??_t types.Gabe Black
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
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