summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2013-06-18ruby: restrict Address to being a type and not a variable nameLena Olson
2013-06-18kvm: Use the address finalization code in the TLBAndreas Sandberg
2013-06-09ruby: remove several unused variables in ProfilerNilay Vaish
2013-06-09ruby: remove periodic event from ProfilerNilay Vaish
2013-06-09ruby: stats: use gem5's stats for cache and memory controllersNilay Vaish
2013-06-09ruby: remove undefined functions in Address classNilay Vaish
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-05-30mem: Make returning snoop responses occupy response layerAndreas Hansson
2013-05-30mem: Make the buses multi layeredAndreas Hansson
2013-05-30mem: Separate the two snoop response cases in the busAndreas Hansson
2013-05-30mem: Tidy up a few variables in the busAndreas Hansson
2013-05-30mem: Add basic stats to the busesUri Wiener
2013-05-30mem: Use unordered set in bus request trackingAndreas Hansson
2013-05-30mem: Check for waiting state in bus drainingAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Adapt the LPDDR2 to match a single x32 channelAndreas Hansson
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21ruby: moesi hammer: cosmetic changesNilay Vaish
2013-05-21ruby: mesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp token: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23sim: Fix two bugs relating to software caching of PageTable entries.Mitch Hayenga
2013-04-23ruby: mesi coherence protocol: remove unused state M_MBNilay Vaish
2013-04-23ruby: patch checkpoint restore with garnetNilay Vaish
2013-04-22mem: Address mapping with fine-grained channel interleavingAndreas Hansson
2013-04-22mem: More descriptive enum names for address mappingAndreas Hansson
2013-04-22mem: Add a WideIO DRAM configurationAndreas Hansson
2013-04-22mem: Adding verbose debug output in the memory systemUri Wiener
2013-04-22mem: Replace check with panic where inhibited should not happenAndreas Hansson
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-17ruby: moesi cmp directory: add copyright noticeNilay Vaish
2013-04-09Ruby: Fix RubyPort evict packet memory leakJoel Hestness
2013-04-09Ruby: Delete packet requests during warmupJoel Hestness
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
2013-04-09Ruby: Order profilers based on versionJoel Hestness
2013-04-09Ruby: More descriptive message buffer connection fatalJason Power
2013-04-09Ruby: Fix typo in Slicc if-statement AST errorJason Power
2013-04-07Ruby System, Cache Recorder: Use delete [] for trace varsJoel Hestness
2013-03-27mem: Fix cache latency bugMitch Hayenga
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-03-26mem: Introduce a variable for the retrying portAndreas Hansson
2013-03-26mem: Add optional request flags to the packet traceAndreas Hansson
2013-03-22ruby: slicc: set sender, receiver clock objs for optional queueNilay Vaish