gem5 - gem5

Age	Commit message (Expand)	Author
2013-11-01	mem: Add tRAS parameter to the DRAM controller model	Ani Udipi
2013-10-31	mem: Add "const" attribute to Packet getters	Stephan Diestelhorst
2013-10-31	mem: Add privilege info to request class	Prakash Ramrakhyani
2013-10-30	ruby: set SenderMachine in messages of MOESI_CMP_directory	Lluc Alvarez
2013-10-30	ruby: Fixed a deadlock when restoring a checkpoint with garnet	Emilio Castillo
2013-10-17	mem: De-virtualise interfaces in the CoherentBus	Stephan Diestelhorst
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	mem: Add PortID to QueuedMasterPort constructor	Sascha Bischoff
2013-10-17	mem: Make MemoryAccess flag more verbose	Ali Saidi
2013-10-15	ruby: eliminate non-determinism from ruby.stats output	Steve Reinhardt
2013-10-15	mem: Rename the ASI_BITS flag field in Request	Andreas Sandberg
2013-10-15	mem: Use a flag instead of address bit 63 for generic IPRs	Andreas Sandberg
2013-09-18	mem: Fix scheduling bug in SimpleMemory	Andreas Hansson
2013-09-11	ruby: Fix Topology throttle connections	Joel Hestness
2013-09-11	ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle	Joel Hestness
2013-09-06	ruby: network: convert to gem5 style stats	Nilay Vaish
2013-09-06	ruby: profiler: removes function resourceUsage()	Nilay Vaish
2013-09-06	ruby: remove undefined message size type	Nilay Vaish
2013-09-06	ruby: network: removes reset functionality	Nilay Vaish
2013-09-06	ruby: network: shorten variable names	Nilay Vaish
2013-09-06	ruby: converts sparse memory stats to gem5 style	Nilay Vaish
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-08-19	stats: Cumulative stats update	Andreas Hansson
2013-08-19	config: Command line support for multi-channel memory	Andreas Hansson
2013-08-19	mem: Change AbstractMemory defaults to match the common case	Andreas Hansson
2013-08-19	mem: Use STL deque in favour of list for DRAM queues	Andreas Hansson
2013-08-19	mem: Perform write merging in the DRAM write queue	Andreas Hansson
2013-08-19	mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM	Amin Farmahini
2013-08-19	mem: Warn instead of panic for tXAW violation	Andreas Hansson
2013-08-19	mem: Allow disabling of tXAW through a 0 activation limit	Andreas Hansson
2013-08-19	mem: Add an internal packet queue in SimpleMemory	Andreas Hansson
2013-08-07	ruby: slicc: remove double trigger, continueProcessing	Nilay Vaish
2013-08-07	ruby: slicc: move some code to AbstractController	Nilay Vaish
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-07-11	ruby: removed the very old double trigger hack	Brad Beckmann
2013-06-28	ruby: append transition comment only when in opt/debug	Nilay Vaish
2013-06-28	ruby: network: remove reconfiguration code	Nilay Vaish
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-27	mem: Tidy up the bridge with const and additional checks	Andreas Hansson
2013-06-27	mem: Fix CommMonitor style and response check	Andreas Hansson
2013-06-27	mem: Align cache timing to clock edges	Andreas Hansson
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-06-27	mem: Remove a redundant heap allocation for a snoop packet	Andreas Hansson
2013-06-27	mem: Remove CoherentBus snoop port unused private member	Andreas Hansson
2013-06-25	ruby: moesi cmp directory: separate actions for external hits	Nilay Vaish
2013-06-25	ruby: mesi cmp directory: separate actions for external hits	Nilay Vaish