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path: root/src/mem
AgeCommit message (Expand)Author
2013-01-07mem: Fix guest corruption when caches handle uncacheable accessesAndreas Sandberg
2013-01-07mem: Remove the IIC replacement policyAndreas Sandberg
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2013-01-07mem: Merge ranges that are part of the conf tableAndreas Hansson
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2013-01-07base: Simplify the AddrRangeMap by removing unused codeAndreas Hansson
2013-01-07mem: Tidy up bus addr range debug messagesAndreas Hansson
2013-01-07mem: Skip address mapper range checks to allow more flexibilityAndreas Hansson
2013-01-07base: Encapsulate the underlying fields in AddrRangeAndreas Hansson
2013-01-07mem: Remove the joining of neighbouring rangesAndreas Hansson
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2013-01-07mem: Add sanity check to packet queue sizeAndreas Hansson
2013-01-07ruby: Fix missing cxx_header in SwitchAndreas Hansson
2013-01-07mem: Fix a bug in the memory serialization file namingAndreas Hansson
2013-01-07cache: add note about where conflicts are handledAli Saidi
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
2012-12-11ruby: add a prefetcherNilay Vaish
2012-12-11ruby: add functions for computing next stride/page addressNilay Vaish
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-10ruby: support functional accesses in garnet flexible networkNilay Vaish
2012-11-10ruby: bug in functionalRead, revert recent changesNilay Vaish
2012-11-08mem: Fix DRAM draining to ensure write queue is emptyAndreas Hansson
2012-11-02ruby: reset and dump stats along with reset of the systemHamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-10-31mem: Fix typo in port commentsAndreas Hansson
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15 ruby: register multiple memory controllersNilay Vaish
2012-10-15ruby: remove AbstractMemOrCacheNilay Vaish
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Mem: Fix incorrect logic in bus blocksize checkAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish