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path: root/src/mem
AgeCommit message (Expand)Author
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Remove legacy DRAM in preparation for memory updatesAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-23Ruby: Fix Set::print for 32-bit hostsAndreas Hansson
2012-03-22MEM: Unify bus access methods and prepare for master/slave splitAndreas Hansson
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-03-19Garnet: Stats at vnet granularity + code cleanupTushar Krishna
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-06build scripts: Made minor modifications to reduce build overhead time.Marc Orr
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-02-29MEM: Make all the port proxy members constAndreas Hansson
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-24MEM: Prepare mport for master/slave splitAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
2012-02-10MESI: Add queues for stalled requestsNilay Vaish
2012-02-09MEM: Remove onRetryList from BusPort and rely on retryListAndreas Hansson
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30Merge with main repository.Gabe Black
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-23MemCmd: Add a command for invalidation requests to LSQNilay Vaish
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson