Age | Commit message (Collapse) | Author |
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
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try to send another packet while it's still waiting for the bus.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
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src/mem/tport.cc:
minor formatting tweak
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
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Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
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extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 4036e8447fb3038d93285c6582900210d7d88d67
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Fix Upgrades being blocked by slave
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
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extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
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src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
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extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
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packet was waiting for the bus.
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extra : convert_revision : 29f7a4f676884330d7b7e93517dea85fc7bbf678
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src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
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extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
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extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
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Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
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extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
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extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
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src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
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src/mem/bus.cc:
Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
Put snooping back into recvTiming and not in it's own function.
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src/mem/physical.cc:
Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
Make memtester have a way to connect functionally
tests/configs/memtest.py:
Properly create 8 memtesters and connect them to the memory system
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extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
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src/mem/cache/cache_impl.hh:
Add more usefull DPRINTF's
REmove the PC to get rid of asserts
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extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
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Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
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src/mem/physical.cc:
Update assertion to check for full range.
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extra : convert_revision : ee815702ba4dd6ae1169c0595c978dd153014c73
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src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
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extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
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If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
Make the fuctional path do the correct tye of snoop
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
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extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
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Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
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extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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code in general.
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src/mem/bus.cc:
src/mem/bus.hh:
minor fix and some formatting changes
src/python/m5/objects/Bus.py:
changed bits to bytes
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
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