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mem
Age
Commit message (
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Author
2013-06-28
ruby: append transition comment only when in opt/debug
Nilay Vaish
2013-06-28
ruby: network: remove reconfiguration code
Nilay Vaish
2013-06-27
mem: Reorganize cache tags and make them a SimObject
Prakash Ramrakhyani
2013-06-27
mem: Remove the cache builder
Andreas Hansson
2013-06-27
sim: Add the notion of clock domains to all ClockedObjects
Akash Bagdia
2013-06-27
config: Remove redundant explicit setting of default clocks
Akash Bagdia
2013-06-27
mem: Tidy up the bridge with const and additional checks
Andreas Hansson
2013-06-27
mem: Fix CommMonitor style and response check
Andreas Hansson
2013-06-27
mem: Align cache timing to clock edges
Andreas Hansson
2013-06-27
mem: Cycles converted to Ticks in atomic cache accesses
Andreas Hansson
2013-06-27
mem: Remove a redundant heap allocation for a snoop packet
Andreas Hansson
2013-06-27
mem: Remove CoherentBus snoop port unused private member
Andreas Hansson
2013-06-25
ruby: moesi cmp directory: separate actions for external hits
Nilay Vaish
2013-06-25
ruby: mesi cmp directory: separate actions for external hits
Nilay Vaish
2013-06-25
ruby: profiler: lots of inter-related changes
Nilay Vaish
2013-06-24
ruby: remove the three files related to profiling
Nilay Vaish
2013-06-24
ruby: MessageBuffer: Remove unused m_size variable
Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-06-20
ruby: fix typo in MOESI_CMP_token protocol
Lena Olson
2013-06-18
ruby: Fix prefetching for MESI_CMP_Directory
Lena Olson
2013-06-18
ruby: fix slicc compiler to complain about duplicate symbols
Lena Olson
2013-06-18
ruby: restrict Address to being a type and not a variable name
Lena Olson
2013-06-18
kvm: Use the address finalization code in the TLB
Andreas Sandberg
2013-06-09
ruby: remove several unused variables in Profiler
Nilay Vaish
2013-06-09
ruby: remove periodic event from Profiler
Nilay Vaish
2013-06-09
ruby: stats: use gem5's stats for cache and memory controllers
Nilay Vaish
2013-06-09
ruby: remove undefined functions in Address class
Nilay Vaish
2013-05-30
mem: More descriptive DRAM config names
Andreas Hansson
2013-05-30
mem: Add bytes per activate DRAM controller stat
Andreas Hansson
2013-05-30
mem: Add static latency to the DRAM controller
Andreas Hansson
2013-05-30
mem: Spring cleaning of MSHR and MSHRQueue
Andreas Hansson
2013-05-30
mem: Fix MSHR print format
Andreas Hansson
2013-05-30
mem: Make returning snoop responses occupy response layer
Andreas Hansson
2013-05-30
mem: Make the buses multi layered
Andreas Hansson
2013-05-30
mem: Separate the two snoop response cases in the bus
Andreas Hansson
2013-05-30
mem: Tidy up a few variables in the bus
Andreas Hansson
2013-05-30
mem: Add basic stats to the buses
Uri Wiener
2013-05-30
mem: Use unordered set in bus request tracking
Andreas Hansson
2013-05-30
mem: Check for waiting state in bus draining
Andreas Hansson
2013-05-30
mem: Add a LPDDR3-1600 configuration
Andreas Hansson
2013-05-30
mem: Adapt the LPDDR2 to match a single x32 channel
Andreas Hansson
2013-05-30
mem: Avoid explicitly zeroing the memory backing store
Andreas Hansson
2013-05-21
ruby: slicc: fix error msg in TypeFieldMemberAST.py
Malek Musleh
2013-05-21
ruby: moesi hammer: cosmetic changes
Nilay Vaish
2013-05-21
ruby: mesi cmp directory: cosmetic changes
Nilay Vaish
2013-05-21
ruby: moesi cmp token: cosmetic changes
Nilay Vaish
2013-05-21
ruby: moesi cmp directory: cosmetic changes
Nilay Vaish
2013-05-21
ruby: add stats to .sm files, remove cache profiler
Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23
sim: Fix two bugs relating to software caching of PageTable entries.
Mitch Hayenga
2013-04-23
ruby: mesi coherence protocol: remove unused state M_MB
Nilay Vaish
2013-04-23
ruby: patch checkpoint restore with garnet
Nilay Vaish
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