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mem
Age
Commit message (
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Author
2015-03-23
mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
Steve Reinhardt
2015-03-23
mem: Tidy up Request
Andreas Hansson
2015-03-19
mem: Use emplace front/back for deferred packets
Andreas Hansson
2015-03-19
mem: Enable CommMonitor to output traces in atomic mode
Geoffrey Blake
2015-02-11
mem: remove redundant test in in Cache::recvTimingResp()
Steve Reinhardt
2015-02-11
mem: add local var in Cache::recvTimingResp()
Steve Reinhardt
2015-02-11
mem: restructure Packet cmd initialization a bit more
Steve Reinhardt
2015-03-14
mem: clean up write buffer check in Cache::handleSnoop()
Steve Reinhardt
2015-03-02
mem: Unify all cache DPRINTF address formatting
Andreas Hansson
2015-03-02
mem: Fix cache MSHR conflict determination
Andreas Hansson
2015-03-02
mem: Add byte mask to Packet::checkFunctional
Andreas Hansson
2015-03-02
mem: Add option to force in-order insertion in PacketQueue
Stephan Diestelhorst
2015-03-02
mem: Downstream components consumes new crossbar delays
Marco Balboni
2015-03-02
mem: Move crossbar default latencies to subclasses
Andreas Hansson
2015-03-02
mem: Add crossbar latencies
Marco Balboni
2015-03-02
mem: Tidy up the cache debug messages
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-03-02
mem: Fix prefetchSquash + memInhibitAsserted bug
Ali Jafri
2015-02-26
Ruby: Update backing store option to propagate through to all RubyPorts
Jason Power
2015-02-16
mem: Fix initial value problem with MemChecker
Stephan Diestelhorst
2015-02-16
mem: mmap the backing store with MAP_NORESERVE
Andreas Hansson
2015-02-16
mem: Use the range cache for lookup as well as access
Andreas Hansson
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2015-02-11
mem: Clarify usage of latency in the cache
Marco Balboni
2015-02-03
mem: Clarify express snoop behaviour
Andreas Hansson
2015-02-03
mem: Clarify cache behaviour for pending dirty responses
Andreas Hansson
2015-02-03
config: Adjust DRAM channel interleaving defaults
Andreas Hansson
2015-01-22
mem: Remove unused Packet src and dest fields
Andreas Hansson
2015-01-22
mem: Remove Packet source from ForwardResponseRecord
Andreas Hansson
2015-01-22
mem: Remove unused RequestState in the bridge
Andreas Hansson
2015-01-22
mem: Always use SenderState for response routing in RubyPort
Andreas Hansson
2015-01-22
mem: Make the XBar responsible for tracking response routing
Andreas Hansson
2015-01-22
mem: Clean up Request initialisation
Andreas Hansson
2015-01-20
mem: Fix bug in cache request retry mechanism
Andreas Hansson
2015-01-20
mem: Move DRAM interleaving check to init
Andreas Hansson
2014-12-23
mem: Change prefetcher to use random_mt
Mitch Hayenga
2014-12-23
mem: Hide WriteInvalidate requests from prefetchers
Curtis Dunham
2014-12-23
mem: Fix event scheduling issue for prefetches
Mitch Hayenga
2014-12-23
mem: Fix bug relating to writebacks and prefetches
Mitch Hayenga
2014-12-23
mem: Rework the structuring of the prefetchers
Mitch Hayenga
2014-12-23
mem: Add parameter to reserve MSHR entries for demand access
Mitch Hayenga
2014-12-23
config: Expose the DRAM ranks as a command-line option
Andreas Hansson
2014-12-23
mem: Ensure DRAM controller is idle when in atomic mode
Andreas Hansson
2014-12-23
mem: Add rank-wise refresh to the DRAM controller
Omar Naji
2014-12-23
mem: Fix a bug in the DRAM controller arbitration
Omar Naji
2014-12-23
mem: Add stack distance statistics to the CommMonitor
Kanishk Sugand
2014-12-23
mem: Add a stack distance calculator
Kanishk Sugand
2014-12-23
mem: Add MemChecker and MemCheckerMonitor
Marco Elver
2014-12-02
mem: Support WriteInvalidate (again)
Curtis Dunham
2014-12-02
mem: Remove WriteInvalidate support
Curtis Dunham
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