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2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-09-09code_formatter: make it easier to insert whitespaceNathan Binkert
a newline by just doing "code()". indent() and dedent() now take a "count" parameter to indent/dedent multiple levels.
2010-09-09cache: fail SC when invalidated while waiting for busSteve Reinhardt
Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too.
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt
We can't just obliviously return the first valid cache block we find any more... see comments for details.
2010-09-09cache: coherence protocol enhancements & bug fixesSteve Reinhardt
Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes.
2010-08-26mem: fix m5.fast compile bug in previous csetSteve Reinhardt
2010-08-25cache: fix a bug in atomic multilevel snoopsSteve Reinhardt
2010-08-25mem: fix dumb typo in copyrightsSteve Reinhardt
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24MOESI_hammer: fixed bug for dma reads in single cpu systemsBrad Beckmann
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches ↵Gene Wu
when it in received
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ↵Gene Wu
the TLB
2010-08-23Compiler: Fixes for GCC 4.5.Ali Saidi
2010-08-20ruby: Added merge GETS optimization to hammerBrad Beckmann
Added an optimization that merges multiple pending GETS requests into a single request to the owner node.
2010-08-20ruby: Stall and wait input messages instead of recyclingBrad Beckmann
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
2010-08-20ruby: Recycle latency fix for hammerBrad Beckmann
Patch allows each individual message buffer to have different recycle latencies and allows the overall recycle latency to be specified at the cmd line. The patch also adds profiling info to make sure no one processor's requests are recycled too much.
2010-08-20MOESI_hammer: break down miss latency stalled cyclesBrad Beckmann
This patch tracks the number of cycles a transaction is delayed at different points of the request-forward-response loop.
2010-08-20ruby: added probe filter support to hammerBrad Beckmann
2010-08-20ruby: fixed DirectoryMemory's numa_high_bit configurationBrad Beckmann
This fix includes the off-by-one bit selection bug for numa mapping.
2010-08-20ruby: Reset ruby stats in RubySystem unserializeBrad Beckmann
The main purpose for clearing stats in the unserialize process is so that the profiler can correctly set its start time to the unserialized value of curTick.
2010-08-20ruby: Disable migratory sharing for token and hammerBrad Beckmann
This patch allows one to disable migratory sharing for those cache blocks that are accessed by atomic requests. While the implementations are different between the token and hammer protocols, the motivation is the same. For Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that have been locked by LL accesses. Therefore, locked blocks should not transfer write permissions when responding to these load requests. Instead, only they only transfer read permissions so that the subsequent SC access can possibly succeed.
2010-08-20ruby: Added SC fail indication to trace profilingBrad Beckmann
2010-08-20ruby: Fixed RubyPort sendTiming callbacksBrad Beckmann
Fixed RubyPort schedSendTiming calls to match ruby frequency.
2010-08-20ruby: fixed token bugs associated with owner token countsBrad Beckmann
This patch fixes several bugs related to previous inconsistent assumptions on how many tokens the Owner had. Mike Marty should have fixes these bugs years ago. :)
2010-08-20ruby: MOESI_CMP_token dma fixesBrad Beckmann
This patch fixes various protocol bugs regarding races between dma requests and persistent requests.
2010-08-20ruby: Resurrected Ruby's deterministic testsBrad Beckmann
Added the request series and invalidate deterministic tests as new cpu models and removed the no longer needed ruby tests --HG-- rename : configs/example/rubytest.py => configs/example/determ_test.py rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20ruby: Updated MOESI_hammer L2 latency behaviorBrad Beckmann
Previously, the MOESI_hammer protocol calculated the same latency for L1 and L2 hits. This was because the protocol was written using the old ruby assumption that L1 hits used the sequencer fast path. Since ruby no longer uses the fast-path, the protocol delays L2 hits by placing them on the trigger queue.
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch.
2010-08-20ruby: fix ruby llsc support to sync sc outcomesBrad Beckmann
Added support so that ruby can determine the outcome of store conditional operations and reflect that outcome to M5 physical memory and cpus.
2010-08-20ruby: Fixed L2 cache miss profilingBrad Beckmann
Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
2010-08-20ruby: Added bcast msg profiling to hammer and tokenBrad Beckmann
2010-08-20ruby: Added consolidated network msg statsBrad Beckmann
2010-08-20ruby: Reincarnated the responding machine profilingBrad Beckmann
This patch adds back to ruby the capability to understand the response time for messages that hit in different levels of the cache heirarchy. Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token protocols.
2010-08-20MOESI_CMP_token: Fixed dma persistent lockdown bugsBrad Beckmann
2010-08-20memtest: Memtester support for DMABrad Beckmann
This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed.
2010-08-20ruby: Added ruby_request_type ostream def to libruby.hhBrad Beckmann
2010-08-20slicc: Consolidated the protocol stats printingBrad Beckmann
Created a separate ProfileDumper that consolidates the generated stats for each controller of a certain type.
2010-08-20config: Added the topology description to m5 config.iniBrad Beckmann
2010-08-20ruby: Fixed printout when Sequencer detects a deadlockBrad Beckmann
2010-08-20MESI_CMP_directory: bug fix for old PUTX requestsBrad Beckmann
2010-08-17bus: clean up default responder code.Steve Reinhardt
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
not scheduled, as well as the transmit list being empty.
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f.
2010-07-08garnet: Added topology print function to Garnet printStatsBrad Beckmann
2010-07-08NetworkMessage copy constructor fixTushar Krishna
2010-06-22style: updated garnet to match M5 coding styleTushar Krishna
2010-06-22cache: fix longstanding prefetcher bugSteve Reinhardt
Thanks to Joe Gross for pointing this out (again?). Apologies to anyone who pointed it out earlier and we didn't listen.
2010-06-16cache: fail store conditionals when upgrade loses raceSteve Reinhardt
Requires new "SCUpgradeReq" message that marks upgrades for store conditionals, so downstream caches can fail these when they run into invalidations. See http://www.m5sim.org/flyspray/task/197
2010-06-16cache: fix dirty bit settingSteve Reinhardt
Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses.
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