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2018-05-30mem-cache: Determine if an MSHR has requests from another cacheNikos Nikoleris
To decide whether we allocate upon receiving a response we need to determine if any of the currently serviced requests (non-deferred targets) is comming from another cache. This change adds support for tracking this information in the MSHR. Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038 Reviewed-on: https://gem5-review.googlesource.com/10422 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-18mem: Add support for more flexible DRAM timing and topologiesWendy Elsasser
This patch has 2 main aspects: 1) Add new parameter to adjust write-to-write delay 2) Enable support of more than 64 banks per controller Changes for new parameter: Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L. This parameter can be used to set a unique delay between writes and between reads. To incorporate this parameter in the controller, modified the DRAMCtrl class to have separate variables for read and write column delays. Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS as well as the new tCCD_L_WR parameter. Changes to support more than 64 banks: Modified the logic selecting the next command (reorderQueue and minBankPrep functions). Replaced the unint64_t variables with a vector of uint32_t elements. There is a uint32_t element defined per ranks to allow up to 32 banks per rank. This will automatically scale with ranks without issue. Change will allow analysis of memory sub-systems beyond the current landscape. Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10103 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-18mem: Optimize self-refresh entryWendy Elsasser
Self-refresh is entered during a refresh event, when the rank was previously in a precharge power-down state. The original code would enter self-refresh after a refresh was issued. The device subsequently will issue a refresh on self-refresh entry. On self-refresh exit, the controller will issue another refresh command. Devices require at least one additional refresh to be issued between self-refresh exit and re-entry. This ensures that enough refreshes occur in the case when the device narrowly missed a refresh on self-refresh exit. To minimize the number of refresh operations and still maintain the device requirement, the current logic does the following: 1) The controller will still enter self-refresh from a refresh event, when the previous state was precharge power-down. However, the refresh itself will be bypassed and the controller will immediately issue a self-refresh entry. 2) On a self-refresh exit, the controller will immediately issue a refresh command (per the original logic). This ensures the devices requirements are met and is a convenient way to kick off the command state machine. Change-Id: I1c4b0dcbfa3bdafd755f3ccd65e267fcd700c491 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10102 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-17mem-cache: Move reference count stats update to blk invalidationNikos Nikoleris
The tags in the cache keep track of the number of references to the blocks as well as the average number of references between an insertion and the next invalidation. Previously the stats where updated only on block insertion and invalidations were ignored. This changes moves the update of the counters to the block invalidation function. Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612 Reviewed-on: https://gem5-review.googlesource.com/10428 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-17mem-cache: Remove isTouched field from the CacheBlkNikos Nikoleris
At the moment isTouched is used in the warm-up detection mechanism but it keeps track of the same information as isValid(). This change removes it and substitutes its use by isValid(). Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62 Reviewed-on: https://gem5-review.googlesource.com/10427 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-17mem-cache: Move replacements stat to the base cache classNikos Nikoleris
Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110 Reviewed-on: https://gem5-review.googlesource.com/10426 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-17mem-cache: Simplify writeback for the tempBlock in recvTimingRespNikos Nikoleris
When we use the tempBlock to fill-in, we have to write it back and invalidate it at the end of current transaction. This patch simplifies the writeback flow by treating it as a regular writeback. Change-Id: I257be7bbff211e2832ad001a4e991daf67704485 Reviewed-on: https://gem5-review.googlesource.com/10421 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-08mem-cache: Create block insertion functionDaniel R. Carvalho
Create a block insertion function to be used when inserting blocks. This resets the number of references to 1 (the insertion is taken into account), sets the insertion tick, and set secure state. Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e Reviewed-on: https://gem5-review.googlesource.com/9824 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-03mem-ruby: Consistent dprintf formats for issue outcomesBrad Beckmann
Change-Id: I053fc42f0d5f678f8e3434b53a0f09e00fc3e345 Reviewed-on: https://gem5-review.googlesource.com/10221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-03mem-cache: Create Second-Chance replacement policyDaniel R. Carvalho
Implementation of a Second-Chance replacement policy. Similar to FIFO, but every block is given a second chance if it has been touched. Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508 Reviewed-on: https://gem5-review.googlesource.com/9441 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-03mem-cache: ReplacementPolicy specific replacement dataDaniel R. Carvalho
Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-26mem-cache: Use block iteration in BaseSetAssocDaniel R. Carvalho
Use block iteration instead of numSets and assoc in print(), cleanupRefs() and computeStats(). This makes these functions rely solely on what they are used for: printing and calculating stats of blocks. With the addition of Sectors an extra indirection level is added, and thus these functions would be skipping blocks. Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32 Reviewed-on: https://gem5-review.googlesource.com/10143 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-19mem-cache: Use findBlock in FALRU's block accessDaniel R. Carvalho
An access must perform a block search, which is done by findBlock. The tagHash is indexed by tags, so use extractTag instead of re- implementing its functionality. Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585 Reviewed-on: https://gem5-review.googlesource.com/10082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-19mem-cache: Use secure flag in FALRU's findBlockDaniel R. Carvalho
FALRU's findBlock() must use the secure flag to assure proper functionality. Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0 Reviewed-on: https://gem5-review.googlesource.com/10081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18mem-cache: Create NRU Replacement PolicyDaniel R. Carvalho
Implementation of a Not Recently Used replacement policy. Change-Id: I24ab3a6f1db6dcb756b869cfebb5c4bc544170e8 Reviewed-on: https://gem5-review.googlesource.com/9001 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-18mem-cache: Revamp multiple size tracking for FALRU cachesNikos Nikoleris
This change fixes a few bugs and refactors the mechanism by which caches that use the FALRU tags can output statistics for multiple cache sizes ranging from the minimum cache of interest up to the actual configured cache size. Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2 Reviewed-on: https://gem5-review.googlesource.com/9826 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-17mem-ruby: enable DPRINTFN calls in slicc for temporary debug printingJohn Alsop
Change-Id: Ib92f8bb4ab7b61ebc96b935cb8abc42cf5ec6ac8 Reviewed-on: https://gem5-review.googlesource.com/9921 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-17mem: Add a helper function to get a word of variable lengthAndreas Sandberg
There are many devices that need to handle reads/writes of different word sizes. A common pattern is a switch statement that check for the size of a packet and then calls the corresponding Packet::(get|set)<uintXX_t> methods. Simplify this by implementing Packet::(get|set)UintX helper functions. The getter reads a word of the size specified in the packet and the specified endianness. The word is then zero-extended to 64 bits. Conversely, the setter truncates the word down to the size required in the packet and then byte-swaps it to the desired endianness. Change-Id: I2f0c27fe3903abf3859bea13b07c7f5f0fb0809f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9761 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-13ruby,gpu-compute: bugfix for GPU_VIPER* protocolsBrandon Potter
12db50c895 changed how directory mapping works, but it seems to have broken the VIPER variants of the GPU protocols. The fix involves declaring the function in the related '.sm' files. Change-Id: I116980d42a4aa648369058b529c9f8d9693eb894 Reviewed-on: https://gem5-review.googlesource.com/8521 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13ruby: bugfix for MESI_Three_Level protocolBrandon Potter
Since a3177645, the MESI_Three_Level protocol does not build. This changeset addresses the problem by adding the L0Cache machine type to the static machine type declaration in Ruby's export file. Change-Id: I6327547fcb34595619caeb73932c0032f5f65c9f Reviewed-on: https://gem5-review.googlesource.com/8383 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-13mem-ruby: fix more style issues in AMD licensesTony Gutierrez
Change-Id: I6585c5664d966989991f61303548aed634cf298a Reviewed-on: https://gem5-review.googlesource.com/9841 Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-13mem-cache: Add MoveToTail to FALRUDaniel R. Carvalho
FALRU was missing MoveToTail functionality within its invalidate function, and MoveToHead was doing unnecessary passes when the moved block was the head already. Besides, added some comments to make the code understandable. Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55 Reviewed-on: https://gem5-review.googlesource.com/9541 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-04-06mem: Remove unused 'using namespace'Daniel R. Carvalho
Removal of unused/barely used 'using namespace' from C++ files. Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a Reviewed-on: https://gem5-review.googlesource.com/9601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Move insertBlock functionality in FALRUDaniel R. Carvalho
Block insertion is being done in the getCandidates function, while the insertBlock function does not do anything. Besides, BaseTags' stats weren't being updated. Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0 Reviewed-on: https://gem5-review.googlesource.com/8882 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create LIP Replacement PolicyDaniel R. Carvalho
Implementation of a LRU Insertion Policy replacement policy. Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44 Reviewed-on: https://gem5-review.googlesource.com/9002 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create BIP Replacement PolicyDaniel R. Carvalho
Implementation of a Bimodal Insertion Policy replacement policy. Change-Id: Ife058d0d4310dbcb35858348006189f0b2bf7c37 Reviewed-on: https://gem5-review.googlesource.com/9003 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-05mem-cache: Use Packet functions to write data blocksDaniel R. Carvalho
Instead of using raw memcpy, use the proper writer functions from the Packet class in Cache. Fixed typos in comments of these functions. Change-Id: I156a00989c6cbaa73763349006a37a18243d6ed4 Reviewed-on: https://gem5-review.googlesource.com/9661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Remove unused return value from the recvTimingReq funcNikos Nikoleris
The recvTimingReq function in the cache always returns true. This changeset removes the return value. Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972 Reviewed-on: https://gem5-review.googlesource.com/8289 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-30mem-cache: Fix FALRU data block seg faultDaniel R. Carvalho
FALRU didn't initialize the blocks' data, causing seg faults. This patch does not make FALRU functional yet. Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b Reviewed-on: https://gem5-review.googlesource.com/9302 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create LFU replacement policyDaniel R. Carvalho
Implementation of a Least Frequently Used replacement policy. Change-Id: I772afccd3a7955777e53d59341e922718db44e5c Reviewed-on: https://gem5-review.googlesource.com/8890 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create RRIP Replacement PolicyDaniel R. Carvalho
Implementation of a Re-Reference Interval Prediction replacement policy. Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b Reviewed-on: https://gem5-review.googlesource.com/8981 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-30mem-cache: Create BRRIP replacement policyDaniel R. Carvalho
Implementation of a Bimodal Re-Reference Interval Prediction replacement policy. Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912 Reviewed-on: https://gem5-review.googlesource.com/8891 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: fix missing overrides in repl policiesJason Lowe-Power
Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9321 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
Added fix in the invalid transition panic and various places in ruby random tester. Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8941 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: Create FIFO replacement policyDaniel R. Carvalho
Implementation of a First-In, First-Out replacement policy. Change-Id: Id234ec9d29c092dd4516e609da14b8a75a96b5e4 Reviewed-on: https://gem5-review.googlesource.com/8888 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: Fix MRU rebaseDaniel R. Carvalho
Rebase of MRU missed a const qualifier, introducing a compilation error. Change-Id: Ia25aa30523613a1a87593a353abe439946656f63 Reviewed-on: https://gem5-review.googlesource.com/9301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Create MRU replacement policyDaniel R. Carvalho
Implementation of a Most Recently Used replacement policy. Change-Id: Id52cb247ca25d4523dcc53490d113695dac6a3f1 Reviewed-on: https://gem5-review.googlesource.com/8889 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-21mem-cache: Allow clean operations when block allocation failsNikos Nikoleris
Block allocation can fail when there is an in-service MSHR that operates on the victim block. This can happed due to: * an upgrade operation: a request that needs a writable copy of the block finds a shared (non-writable) copy of the block in the cache and has allocates an MSHR for the pending upgrade operation, or * a clean operation: a clean request finds a dirty copy of the block and allocates an MSHR for the pending clean operation. This changes relaxes an assertion to allow for the 2nd case (cache clean operations). Change-Id: Ib51482160b5f2b3702ed744b0eac2029d34bc9d4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-12mem-ruby: Fix RubyPrefetcher support in MESI_Two_LevelRico Amslinger
Only a small quantity of prefetches were issued, as the positive feedback mechanism was not implemented. This commit adds a new action po_observeHit, which notifies the RubyPrefetcher of successful prefetches and resets the prefetch flag. When a cache line was replaced by a prefetch, the wrong queue could be stalled. This commit adds a new event PF_L1_Replacement, which stalls the correct queue. The behavior when receiving a prefetch or instruction fetch while in PF_IS_I (prefetch caused GETs, but got invalidated before the response was received) was undefined. This was changed to drop the prefetch request or change the state to non-prefetch, respectively. This behavior is analogous to IS_I (non-prefetch caused GETs, but got invalidated before the response was received) and the data case, respectively. In my local branch a major (20+%) performance increase can be observed in SPEC2006 gobmk and leslie3d when enabling the prefetcher. Some other benchmarks like bwaves, GemsFDTD, sphinx and wrf show smaller (~10%) performance increases. Unfortunately, the performance in most other SPEC benchmarks is still poor, most likely as the prefetcher does not detect strides fast/often enough. In order to push the change timely (most benchmarks have runtimes in the order of days on my machine even with the smallest parameters) after checkout, I have only run gobmk with the base repository + this commit. The results match those of my local branch. Change-Id: I9903a2fcd02060ea5e619b409f31f7d6fac47ae8 Reviewed-on: https://gem5-review.googlesource.com/8801 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Swapnil Haria <swapnilster@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-09mem-cache: Use CacheBlk parameter on address regenerationDaniel R. Carvalho
Skewed caches need to know the way to regenerate a block address. Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40 Reviewed-on: https://gem5-review.googlesource.com/8782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08mem-cache: Fix missing overridesJason Lowe-Power
clang doesn't like inconsistent overrides. Add override to all overidden functions in lru.hh Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8861 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Make the block invalidate functions virtualNikos Nikoleris
This change makes the cache block invalidation function in the BaseTags and CacheBlk class virtual to enable derived classes. Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8287 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-07mem-cache: Make invalidate a common function between tag classesNikos Nikoleris
invalidate was defined as a separate function in the base associative and fully-associative tags classes although both functions should implement identical functionality. This patch moves the invalidate function in the base tags class. Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8286 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Allow prefetchers to override setCache.Xiaoyu Ma
This lets them hook setCache, perhaps to set up additional state based on the set cache. Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27 Reviewed-on: https://gem5-review.googlesource.com/8701 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06mem-cache: Fix bug generated by 8282Daniel R. Carvalho
Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated a bug in tagsInUse calculation. Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b Reviewed-on: https://gem5-review.googlesource.com/8781 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>