Age | Commit message (Collapse) | Author |
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SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
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The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
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way so a cache can handle partial block requests for i/o devices.
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Improve MRU checking for StaticInst, Bus, TLB
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Make sure not to keep processing functional accesses
after they've been responded to.
Also use checkFunctional() return value instead of checking
packet command field where possible, mostly just for consistency.
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Also make express snoops not occupy bus (since they're magic).
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(now that bus no longer filters them for us).
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Also some additional cleanup of Bus::recvTiming().
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
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extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
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based on following Packet senderState links.
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Turns out DeferredSnoop isn't quite the right bit of info
we needed... see new comment in cache_impl.hh.
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If the invalidation beats the upgrade at a lower level
then the upgrade must be converted to a read exclusive
"in the field".
Restructure target list & deferred target list to
factor out some common code.
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extra : convert_revision : 7bab4482dd6c48efdb619610f0d3778c60ff777a
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- Add "deferred snoop" flag to Packet so upper-level caches
can distinguish whether lower-level cache request was
in-service or not at the time of the original snoop.
- Revamp response handling to properly handle deferred snoops
on non-cache-fill requests (i.e. upgrades).
- Make sure forwarded writebacks are kept in write buffer at
lower-level caches so they get snooped properly.
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Atomic mode seems to work. Timing is closer but not there yet.
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Move check for loops outside, since half the call sites
end up working around it anyway. Return integer port ID
instead of port object pointer.
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Note that we should *not* print pointer values in DPRINTFs as
these needlessly clutter tracediff output.
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src/cpu/simple/timing.cc:
Fix another SC problem.
src/mem/cache/cache_impl.hh:
Forgot to call makeTimingResponse() on uncached timing responses.
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extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
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src/cpu/simple/timing.cc:
Fix swap/stq_c command bug.
src/mem/packet.cc:
Fix incorrect LoadLockedReq command response field.
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extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
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Fix atomic timing issue.
src/mem/bus.cc:
Fix atomic timing issue.
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Handled by Packet::checkFunctional() now.
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(they function as adjectives not nouns)
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Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
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