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path: root/src/mem
AgeCommit message (Expand)Author
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-03ruby: Implement SwapReq supportMarco Elver
2016-05-26mem: Fix memory leak in handling of deferred snoopsAndreas Hansson
2016-05-26mem: Do not set cacheResponding on MSHR snoop if not respondingAndreas Hansson
2016-05-26mem: Fix MemChecker unique_ptr type mismatchAndreas Hansson
2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
2016-05-26mem: remove redudant check whether the cache forwards snoopsNikos Nikoleris
2016-05-26mem: change NULL to nullptr in the cache related classesNikos Nikoleris
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
2016-04-26ruby: Rename pkt to m_pkt so it may be accessed via SLICCMatthew Poremba
2016-04-21mem: Include WriteLineReq in cache demand statsAndreas Hansson
2016-04-21mem: Remove unused cache statsAndreas Hansson
2016-04-21mem: Deallocate all write-queue entries when sentAndreas Hansson
2016-04-21mem: Align downstream cache packet creation in atomic and timingAndreas Hansson
2016-04-15ruby: Fix block_on behaviorJoel Hestness
2016-04-15mem: FreeBSD does not provide MAP_NORESERVE eitherBjoern A. Zeeb
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
2016-04-07mem: Add priority to QueuedPrefetcherRekai Gonzalez Alberquilla
2016-04-07mem: Handful extra features for BasePrefetcherRekai Gonzalez Alberquilla
2016-04-07mem: Add Program Counter to MemTraceProbeVictor Garcia
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
2016-03-17mem: Adjust cache queue reserve to more conservative valuesAndreas Hansson
2016-03-17mem: Create a separate class for the cache write bufferAndreas Hansson
2015-08-10mem, cpu: Add assertions to snoop invalidation logicStephan Diestelhorst
2016-02-24mem: Ensure that InvalidateReq is not forwarded as ReadExReqAndreas Hansson
2016-02-23scons: Add missing override to appease clangAndreas Hansson
2016-02-18ruby: move range change send from RubyPort to derived classes.Tony Gutierrez
2016-02-17ruby: send address ranges from RubyPortTony Gutierrez
2016-02-15misc: Add missing overrides to appease clangAndreas Hansson
2016-02-15mem: Avoid using invalid iterator in cache lock list traversalAndreas Hansson
2016-02-14ruby: make DMASequencer inherit from RubyPortMichael LeBeane
2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
2016-01-19* * *Tony Gutierrez
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