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path: root/src/mem
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2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-06-27mem: Tidy up the bridge with const and additional checksAndreas Hansson
2013-06-27mem: Fix CommMonitor style and response checkAndreas Hansson
2013-06-27mem: Align cache timing to clock edgesAndreas Hansson
2013-06-27mem: Cycles converted to Ticks in atomic cache accessesAndreas Hansson
2013-06-27mem: Remove a redundant heap allocation for a snoop packetAndreas Hansson
2013-06-27mem: Remove CoherentBus snoop port unused private memberAndreas Hansson
2013-06-25ruby: moesi cmp directory: separate actions for external hitsNilay Vaish
2013-06-25ruby: mesi cmp directory: separate actions for external hitsNilay Vaish
2013-06-25ruby: profiler: lots of inter-related changesNilay Vaish
2013-06-24ruby: remove the three files related to profilingNilay Vaish
2013-06-24ruby: MessageBuffer: Remove unused m_size variableJoel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-06-20ruby: fix typo in MOESI_CMP_token protocolLena Olson
2013-06-18ruby: Fix prefetching for MESI_CMP_DirectoryLena Olson
2013-06-18ruby: fix slicc compiler to complain about duplicate symbolsLena Olson
2013-06-18ruby: restrict Address to being a type and not a variable nameLena Olson
2013-06-18kvm: Use the address finalization code in the TLBAndreas Sandberg
2013-06-09ruby: remove several unused variables in ProfilerNilay Vaish
2013-06-09ruby: remove periodic event from ProfilerNilay Vaish
2013-06-09ruby: stats: use gem5's stats for cache and memory controllersNilay Vaish
2013-06-09ruby: remove undefined functions in Address classNilay Vaish
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-05-30mem: Make returning snoop responses occupy response layerAndreas Hansson
2013-05-30mem: Make the buses multi layeredAndreas Hansson
2013-05-30mem: Separate the two snoop response cases in the busAndreas Hansson
2013-05-30mem: Tidy up a few variables in the busAndreas Hansson
2013-05-30mem: Add basic stats to the busesUri Wiener
2013-05-30mem: Use unordered set in bus request trackingAndreas Hansson
2013-05-30mem: Check for waiting state in bus drainingAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Adapt the LPDDR2 to match a single x32 channelAndreas Hansson
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21ruby: moesi hammer: cosmetic changesNilay Vaish
2013-05-21ruby: mesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp token: cosmetic changesNilay Vaish
2013-05-21ruby: moesi cmp directory: cosmetic changesNilay Vaish
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23sim: Fix two bugs relating to software caching of PageTable entries.Mitch Hayenga
2013-04-23ruby: mesi coherence protocol: remove unused state M_MBNilay Vaish
2013-04-23ruby: patch checkpoint restore with garnetNilay Vaish
2013-04-22mem: Address mapping with fine-grained channel interleavingAndreas Hansson
2013-04-22mem: More descriptive enum names for address mappingAndreas Hansson