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2007-03-27Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 45b64b1564f0e4958d8441455f87b2b185324d55
2007-03-27First Pass At Cmp/Swap in cachesRon Dreslinski
--HG-- extra : convert_revision : 211bfb7c6a59e9e120dae1600d4754baaf231332
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-233 memory system fixes:Kevin Lim
1. Update packet's flags properly when a snoop happens 2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data). 3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list. src/mem/bus.cc: Update packet's flags properly upon snoop. src/mem/cache/cache_impl.hh: Be sure to not allow accesses to a block with outstanding MSHRs. src/mem/cache/miss/miss_queue.cc: Update MSHR's request upon a response being handled. --HG-- extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
2007-03-12Clean up more memory leaksRon Dreslinski
--HG-- extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3
2007-03-12Fix some of the memory leaks related to writebacksRon Dreslinski
src/cpu/memtest/memtest.cc: Add the [] to a delete to make it work correctly src/mem/cache/cache_impl.hh: Fix one of the memory leaks --HG-- extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-09Two fixes:Kevin Lim
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed. This is done by making setPeer() virtual, and overriding it in the CPU's ports. When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts(). 2. Consolidate redundant code that handles switching in a CPU. src/cpu/base.cc: Move common code of switching over peers to base CPU. src/cpu/base.hh: Move common code of switching over peers to BaseCPU. src/cpu/o3/cpu.cc: Add in function that updates thread context's ports. Also use updated function to takeOverFrom() in BaseCPU. This gets rid of some repeated code. src/cpu/o3/cpu.hh: Include function to update thread context's memory ports. src/cpu/o3/lsq.hh: Add function to dcache port that will update the memory ports upon getting a new peer. Also include a function that will tell the CPU to update those memory ports. src/cpu/o3/lsq_impl.hh: Add function that will update the memory ports upon getting a new peer. src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Add function that will update thread context's memory ports upon getting a new peer. Also use the new BaseCPU's take over from function. src/cpu/simple/atomic.hh: Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer. src/cpu/simple/timing.hh: Add function that will update thread context's memory ports upon getting a new peer. src/mem/port.hh: Make setPeer virtual so that other classes can override it. --HG-- extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
2007-03-08stop m5 from leaking like a sieveAli Saidi
don't create a new physPort/virtPort every time activateContext() is called add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs() on the port owner as well as delete it's peer still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic src/cpu/thread_state.cc: if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it src/mem/bus.cc: src/mem/bus.hh: add ability to delete a port by usig a hash_map instead of an array to store port ids add a function to do deleting src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/mem_object.cc: src/mem/mem_object.hh: adda function to delete port references from a memory object src/mem/port.cc: src/mem/port.hh: add a removeConn function that tell the owener to delete any references to the port and then deletes its peer --HG-- extra : convert_revision : 272f0c8f80e1cf1ab1750d8be5a6c9aa110b06a4
2007-03-07Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same ↵Gabe Black
across all architectures. --HG-- extra : convert_revision : 18d441eb7ac44df4df41771bfe3dec69f7fa70ec
2007-03-07Make byteswap work correctly on Twin??_t types.Gabe Black
--HG-- extra : convert_revision : a8a14078d62c24e480ffa69591edfc775d1d76cc
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way ↵Ali Saidi
as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-02-18implement vtophys and 32bit gdb supportAli Saidi
src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/sparc/arguments.hh: move Copy* to vport since it's generic for all the ISAs src/arch/sparc/isa_traits.hh: the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase src/arch/sparc/pagetable.hh: add a class for getting bits out of the TteTag src/arch/sparc/remote_gdb.cc: add 32bit support kinda.... If its 32 bit src/arch/sparc/remote_gdb.hh: Add 32bit register offsets too. src/arch/sparc/tlb.cc: cleanup generation of tsb pointers src/arch/sparc/tlb.hh: add function to return tsb pointers for an address make lookup public so vtophys can use it src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: write vtophys for sparc src/base/bitfield.hh: return a mask of bits first->last src/mem/vport.cc: src/mem/vport.hh: move Copy* here since it's ISA generic --HG-- extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
2007-02-12some forgotten commitsAli Saidi
--HG-- extra : convert_revision : 213440066c700ed5891a6d4568928b7f3f2fe750
2007-02-12rename store conditional stuff as extra data so it can be used for ↵Ali Saidi
conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-07Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-06More DPRINTF cleanup.Steve Reinhardt
--HG-- extra : convert_revision : db89cea42b46476d19333038522a6c144eafdab1
2007-02-06Include compiler.hh since we use some of the #definesNathan Binkert
--HG-- extra : convert_revision : 1040addcf3f52d8d9fed2930890dadf524205af9
2007-02-06Minor DPRINTF fixes.Steve Reinhardt
--HG-- extra : convert_revision : 41956c9a480163ecac7807982215027e8ff1a4a9
2007-02-06Fix for LL/SC that Ron sent me.Kevin Lim
--HG-- extra : convert_revision : b3510a23d8a9eb466939f38491a109c3a65a7363
2007-01-27While I'm waiting for legion to run make m5 compile with a few more compilersAli Saidi
SConstruct: src/SConscript: Add flags for Intel CC while i'm at it src/base/compiler.hh: the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way src/base/cprintf_formats.hh: add std:: where appropriate src/base/statistics.hh: use this->map since icc was getting confused about std::map vs the locally defined map src/cpu/static_inst.hh: Add some more dummy returns where needed src/mem/packet.hh: add more dummy returns where needed src/sim/host.hh: use limits to come up with max tick --HG-- extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
2007-01-26make our code a little more standards compliantAli Saidi
pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2006-12-27Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
--HG-- extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
don't regenerate address from block in cache so that tags can turn around and use address to look up block again. --HG-- extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
--HG-- rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
--HG-- extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-15Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15Use my range_map to speed up findPort() in the bus. The snoop code could ↵Ali Saidi
still use some work. --HG-- extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). --HG-- extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-06Many more fixes for SPARC_FS. Gets us to the point where SOFTINT startsAli Saidi
getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-05Don't compress data on writebacks unless it's actually necessary.Steve Reinhardt
--HG-- extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
2006-12-04Turn cache MissQueue/BlockingBuffer into virtual objectSteve Reinhardt
instead of template parameter. --HG-- extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
2006-12-02Make cache compression policy a runtime virtual thingSteve Reinhardt
instead of a template policy. --HG-- extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
2006-11-29Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmemmid src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.hh: hand merge --HG-- extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
2006-11-29Add support for mmapped iprs to atomic cpuAli Saidi
src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits --HG-- extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
2006-11-28Remove assertion. It's not needed and messes up writebacks when a 2 level ↵Kevin Lim
cache is used in a uniprocessor setting. --HG-- extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
2006-11-24Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
2006-11-23Merge zizzer:/bk/sparcfsAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
2006-11-23first cut at a sparc tlbAli Saidi
src/arch/sparc/SConscript: Add code to serialize/unserialze tlb entries src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: update asi names for how they're listed in the supplement add asis add more asi functions src/arch/sparc/isa_traits.hh: move the interrupt stuff and some basic address space stuff into isa traits src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add mmu registers to tlb get rid of implicit asi stuff... the tlb will handle it src/arch/sparc/regfile.hh: make isnt/dataAsid return ints not asis src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: first cut at sparc tlb src/arch/sparc/vtophys.hh: pagatable nedes to be included here src/mem/request.hh: add asi and if the request is a memory mapped register to the requset object src/sim/host.hh: fix incorrect definition of LL --HG-- extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ↵Gabe Black
we can make our own hypervisor binary, we probably won't need it. --HG-- extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
2006-11-22Do a functional access to levels above on a read as a temporary solution for ↵Ron Dreslinski
L2's in FS Fix a small writeback bug when missing in the L2 in atomic mode src/mem/bus.cc: Fix a comment to make sense src/mem/cache/cache_impl.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS Also fix a small writeback miss in L2 issue src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: Update ref's for writeback changes --HG-- extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
2006-11-20Fix an assert to correctly make sure a request falls entirely inside a memory.Gabe Black
--HG-- extra : convert_revision : 71cf02edffbc7029666c0d9c97b67e1d32332758
2006-11-14Fix bugs around uni-coherence invalidates being propogated properly.Ron Dreslinski
src/mem/bus.cc: Make it so that invalidates being sent from the responder up don't call the responder but they should also not Panic. src/mem/packet.hh: If we don't have data in the packet, don't call deleteData: Example: InvalidateRequests never have data. --HG-- extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
2006-11-14Update atomic and functional paths for snoops as wellRon Dreslinski
--HG-- extra : convert_revision : 566d73438efb87ca683e4dee23454d880db3dfc7
2006-11-14Update bus bridges now that snoop ranges are passed properlyRon Dreslinski
src/mem/bridge.cc: Update brdiges, now that snoop addresses are properly forwarded. Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT) src/mem/bus.cc: src/mem/bus.hh: Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once --HG-- extra : convert_revision : 26cc9ee4429be45d4476fa435e0e9a54843c2509
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