index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem
Age
Commit message (
Expand
)
Author
2006-07-20
Move PioPort timing code into Simple Timing Port object
Ali Saidi
2006-07-10
Some fixes so that MSHR's are matched and we don't issue overlapping requests...
Ron Dreslinski
2006-07-10
Fix offset calculation. Now L2's work with timing&atomic.
Ron Dreslinski
2006-07-07
Fix address range calculation. Still need bus to handle snoop ranges.
Ron Dreslinski
2006-07-07
Update cpus to use the getPort function to use a connector object to connect ...
Ron Dreslinski
2006-07-06
Timing cache works for hello world test.
Ron Dreslinski
2006-07-06
Merge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski
2006-07-06
Now timing reads work in single level of cache with simple cpu
Ron Dreslinski
2006-07-06
Add default responder to bus
Ali Saidi
2006-07-05
Fix some unset values in the request in the timing CPU.
Ron Dreslinski
2006-06-30
AtomicSimpleCPU with a cache now runs the hello world! test program.
Ron Dreslinski
2006-06-30
First pass, now compiles with current head of tree.
Ron Dreslinski
2006-06-30
Fix the packet data allocation methods. Small fixes from changesets after my...
Ron Dreslinski
2006-06-30
Merge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski
2006-06-30
All files compile in the mem directory except cache_builder
Ron Dreslinski
2006-06-29
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-06-29
Still missing prefetch and tags directories as well as cache builder.
Ron Dreslinski
2006-06-28
More Changes, working towards cache.cc compiling. Headers cleaned up.
Ron Dreslinski
2006-06-28
Backing in more changsets, getting closer to compile
Ron Dreslinski
2006-06-28
Was having difficulty with merging the cache, reverted to an early version an...
Ron Dreslinski
2006-06-27
change the page table from map to hash_map and create small cache to to speed...
Ali Saidi
2006-06-26
add syscall emulation page table fault so we can allocate more stack pages
Ali Saidi
2006-06-25
Allow ports to be created without a name.
Kevin Lim
2006-06-17
minor header cleanups
Ali Saidi
2006-06-13
Move SimObject creation and Port connection loops
Steve Reinhardt
2006-06-08
add nacked result and a function to swizzle nacked packet into something that...
Ali Saidi
2006-06-08
add write/read functions that have endian conversions in them
Ali Saidi
2006-06-06
Change ExecContext to ThreadContext. This is being renamed to differentiate ...
Kevin Lim
2006-06-06
Fix checker to work in newmem in SE mode.
Kevin Lim
2006-06-02
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-06-02
Fixes to get compiling to work. This is mainly fixing up some includes; chan...
Kevin Lim
2006-05-31
Updated Authors from bk prs info
Ali Saidi
2006-05-31
Streamline interface to Request object.
Steve Reinhardt
2006-05-30
Minor further cleanup & commenting of Packet class.
Steve Reinhardt
2006-05-30
Fix Port pointer initialization.
Steve Reinhardt
2006-05-30
Add a very poor implementation of dealing with retries on timing requests. It...
Ali Saidi
2006-05-26
Reorganize bridge as pair of cooperating ports.
Steve Reinhardt
2006-05-26
Add a little more tracing support for Bus/Port stuff.
Steve Reinhardt
2006-05-26
Significant rework of Packet class interface:
Steve Reinhardt
2006-05-26
Add names to memory Port objects for tracing.
Steve Reinhardt
2006-05-23
Minor fixes for full-system timing memory.
Steve Reinhardt
2006-05-22
New directory structure:
Steve Reinhardt
[prev]