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is-rebase07-GCC8
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mem
Age
Commit message (
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Author
2012-05-09
MEM: Add the communication monitor
Andreas Hansson
2012-05-08
MEM: Do not forward uncacheable to bus snoopers
Andreas Hansson
2012-05-04
Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
Andreas Hansson
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-28
Garnet: Correct computation of link utilization
Nilay Vaish
2012-04-25
Ruby: Remove extra statements from Sequencer
Nilay Vaish
2012-04-25
MEM: Use base class Master/SlavePort pointers in the bus
Andreas Hansson
2012-04-25
MEM: Add the PortId type and a corresponding id field to Port
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-04-14
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
Andreas Hansson
2012-04-12
Ruby: Ensure order-dependent iteration uses an ordered map
Andreas Hansson
2012-04-06
slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
Lisa Hsu
2012-04-06
sim-ruby: checkpointing fixes and dependent eventq improvements
Brad Beckmann
2012-04-06
slicc: fixed error message when the type has no inheritance
Brad Beckmann
2012-04-06
MOESI_hammer: tbe allocation and dependent wakeup fixes
Brad Beckmann
2012-04-06
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi...
Brad Beckmann
2012-04-06
rubytest: seperated read and write ports.
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-03-30
MEM: Remove legacy DRAM in preparation for memory updates
Andreas Hansson
2012-03-30
Ruby: Remove the physMemPort and instead access memory directly
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-23
Ruby: Fix Set::print for 32-bit hosts
Andreas Hansson
2012-03-22
MEM: Unify bus access methods and prepare for master/slave split
Andreas Hansson
2012-03-22
MEM: Split SimpleTimingPort into PacketQueue and ports
Andreas Hansson
2012-03-22
Scons: Remove Werror=False in SConscript files
Andreas Hansson
2012-03-19
Garnet: Stats at vnet granularity + code cleanup
Tushar Krishna
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-03-06
build scripts: Made minor modifications to reduce build overhead time.
Marc Orr
2012-03-02
Ruby: Rename RubyPort::sendTiming to avoid overriding base class
Andreas Hansson
2012-03-01
Cache: Fix an issue with LRU when bonus block is used to complete transaction.
Ali Saidi
2012-02-29
MEM: Make all the port proxy members const
Andreas Hansson
2012-02-24
MEM: Simplify cache ports preparing for master/slave split
Andreas Hansson
2012-02-24
MEM: Prepare mport for master/slave split
Andreas Hansson
2012-02-24
MEM: Move all read/write blob functions from Port to PortProxy
Andreas Hansson
2012-02-24
MEM: Make port proxies use references rather than pointers
Andreas Hansson
2012-02-24
MEM: Move port creation to the memory object(s) construction
Andreas Hansson
2012-02-24
CPU: Round-two unifying instr/data CPU ports across models
Andreas Hansson
2012-02-24
MEM: Fatal when no port can be found for an address
Andreas Hansson
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-02-12
prefetcher: Make prefetcher a sim object instead of it being a parameter on c...
Mrinmoy Ghosh
2012-02-10
Ruby: Remove isTagPresent() calls from Sequencer.cc
Nilay Vaish
2012-02-10
MESI: Add queues for stalled requests
Nilay Vaish
2012-02-09
MEM: Remove onRetryList from BusPort and rely on retryList
Andreas Hansson
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-31
MEM: Remove the otherPort from the cache ports
Andreas Hansson
2012-01-31
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Geoffrey Blake
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