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2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system.
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
CopyStringOut() improperly indexed setting the null character, would result in zeroing a random byte of memory after(out of bounds) the character array.
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU.
2012-01-23MemCmd: Add a command for invalidation requests to LSQNilay Vaish
This command will be sent from the memory system (Ruby) to the LSQ of an O3 CPU so that the LSQ, if it needs to, invalidates the address in the request packet.
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
This patch removes the idiosyncratic nature of the default bus port and makes it yet another port in the list of interfaces. Rather than having a specific pointer to the default port we merely track the identifier of this port. This change makes future port diversification easier and overall cleans up the bus code.
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
The functional ports are no longer used and this patch cleans up the legacy that is still present in buses, memories, CPUs etc. Note that this does not refer to the class FunctionalPort (already removed), but rather ports with the name (and use) functional.
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
This patch simplifies the address-range determination mechanism and also unifies the naming across ports and devices. It further splits the queries for determining if a port is snooping and what address ranges it responds to (aiming towards a separation of cache-maintenance ports and pure memory-mapped ports). Default behaviours are such that most ports do not have to define isSnooping, and master ports need not implement getAddrRanges.
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
Cleaning up and simplifying the ports and going towards a more strict elaboration-time creation and binding of the ports.
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
This patch removes the default port and instead relies on the peer being set to NULL initially. The binding check (i.e. is a port connected or not) will eventually be moved to the init function of the modules.
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
This patch removes the inheritance of EventManager from the ports and moves all responsibility for event queues to the owner. Eventually the event manager should be the interface block, which could either be the structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
This patch changes the access permission for the WB_E_W state from Busy to Read_Write to avoid having issues in follow-on patches with functional accesses going through Ruby. This change was made after consultation with all involved parties and is more of a work-around than a fix.
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
This patch changes the functionalAccess member function in the cache model such that it is aware of what port the access came from, i.e. if it came from the CPU side or from the memory side. By adding this information, it is possible to respect the 'forwardSnoops' flag for snooping requests coming from the memory side and not forward them. This fixes an outstanding issue with the IO bus getting accesses that have no valid destination port and also cleans up future changes to the bus model.
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
The definition for the class CacheMsg was removed long back. Some declaration had still survived, which was recently removed. Since the PerfectCacheMemory class relied on this particular declaration, its absence let to compilation breaking down. Hence this patch.
2012-01-11Packet: Put back part of the assertAli Saidi
2012-01-11Packet: Remove meaningless assert statementAli Saidi
2012-01-11Ruby: Resurrect Cache Warmup CapabilityNilay Vaish
This patch resurrects ruby's cache warmup capability. It essentially makes use of all the infrastructure that was added to the controllers, memories and the cache recorder.
2012-01-11Ruby Debug Flags: Remove one, add anotherNilay Vaish
The flag RubyStoreBuffer is being removed, instead RubySystem is being added
2012-01-11Ruby Port: Add a list of cpu ports attached to this portNilay Vaish
2012-01-11Ruby EventQueue: Remove unused functionsNilay Vaish
2012-01-11Ruby Sparse Memory: Add function for collating blocksNilay Vaish
This patch adds function to the Sparse Memory so that the blocks can be recorded in a cache trace. The blocks are added to the cache recorder which can later write them into a file.
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
This patch changes CacheRecorder, CacheMemory, CacheControllers so that the contents of a cache can be recorded for checkpointing purposes.
2012-01-11Ruby Memory Vector: Functions for collating and populating pagesNilay Vaish
This patch adds functions to the memory vector class that can be used for collating memory pages to raw trace and for populating pages from a raw trace.
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
The Ruby Tracer is out of date with the changes that are being carried out to support checkpointing. Hence, it needs to be removed.
2012-01-10MOESI Hammer: Remove a couple of bugsNilay Vaish
A couple of bugs were observed while building checkpointing support in Ruby. This patch changes transitions to remove those errors.
2012-01-10Sparse Memory: Simplify the structure for an entryNilay Vaish
The SparseMemEntry structure includes just one void* pointer. It seems unnecessary that we have a structure for this. The patch removes the structure and makes use of a typedef on void* instead.
2012-01-09Packet: Add derived class FunctionalPacket to enable partial functional readsGeoffrey Blake
This adds the derived class FunctionalPacket to fix a long standing deficiency in the Packet class where it was unable to handle finding data to partially satisfy a functional access. Made this a derived class as functional accesses are used only in certain contexts and to not add any additional overhead to the existing Packet class.
2012-01-09mem: Change DPRINTF prints more useful destination port number.Min Kyu Jeong
Old code prints 0 for destination since pkt->getDest() returns 0 for pkt->getDest() == Packet::Broadcast, which is always true.
2012-01-07Ruby Cache: Add param for marking caches as instruction onlyNilay Vaish
2012-01-06AbstractController: Remove some of the unused functionsNilay Vaish
--HG-- extra : rebase_source : 78df7398a609f1db8a2592cd2d1bdc9156d1b8c3
2012-01-06Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hhNilay Vaish
This constant is currently in System.hh, but is only used in Set.hh. It is being moved to Set.hh to remove this artificial dependence of Set.hh on System.hh. --HG-- extra : rebase_source : 683c43a5eeaec4f5f523b3ea32953a07f65cfee7
2012-01-05MESI Coherence Protocol: Fix L2 miss statisticsNilay Vaish
This patch removes calls to uu_ProfileMiss from transitions where the request is satisfied by the L2 cache controller. --HG-- extra : rebase_source : e59fe7c6cd5795c0019cf178dd3b062d73cc2ff5
2011-12-31Ruby: Shuffle some of the included filesNilay Vaish
This patch adds and removes included files from some of the files so as to organize remove some false dependencies and include some files directly instead of transitively. --HG-- extra : rebase_source : 09b482ee9ae00b3a204ace0c63550bc3ca220134
2011-12-31SLICC: Use pointers for directory entriesNilay Vaish
SLICC uses pointers for cache and TBE entries but not for directory entries. This patch changes the protocols, SLICC and Ruby memory system so that even directory entries are referenced using pointers. --HG-- extra : rebase_source : abeb4ac78033d003153751f216fd1948251fcfad
2011-12-13gcc: fix unused variable warnings from GCC 4.6.1Nathan Binkert
--HG-- extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-01MOESI_hammer: fixed L2 to L1 infinite stalls and deadlockBrad Beckmann
--HG-- extra : rebase_source : 90f217f28e195a8cee5d64b25c913b452d818676
2011-12-01physmem: Improved fatal message for size mismatchBrad Beckmann
--HG-- extra : rebase_source : 16da1c63263f8fd6fef9a842c577343cd6246a35
2011-11-23Topology: bug fix in external link initializationTushar Krishna
--HG-- extra : rebase_source : c226cd1e5e5ed4d4c64fa9427de4905bd8335e34
2011-11-22Remove standard_1level_CMP-protocol.sm include statement from NetworkTushar Krishna
--HG-- extra : rebase_source : 51a2dd4bb643e3dc5b0218a6190cf5c1989f9691
2011-11-14Ruby: Process packet instead of RubyRequest in SequencerNilay Vaish
This patch changes the implementation of Ruby's recvTiming() function so that it pushes a packet in to the Sequencer instead of a RubyRequest. This requires changes in the Sequencer's makeRequest() and issueRequest() functions, as they also need to operate on a Packet instead of RubyRequest.
2011-11-04GARNET: adding a fault model for resilient on-chip network research.Tushar Krishna
This patch adds a fault model, which provides the probability of a number of architectural faults in the interconnection network (e.g., data corruption, misrouting). These probabilities can be used to realistically inject faults in GARNET and faithfully evaluate the effectiveness of novel resilient NoC architectures.
2011-11-04MESI Protocol: Add functions for profiling missesNilay Vaish
2011-11-03Protocol: Remove standard one and two level filesNilay Vaish
2011-11-03Ruby: Remove some unused typedefsNilay Vaish
This patch removes some of the unused typedefs. It also moves some of the typedefs from Global.hh to TypeDefines.hh. The patch also eliminates the file NodeID.hh.
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
And by "everything" I mean all the quick regressions.
2011-10-28Merged with recent changes.Nilay Vaish
2011-10-28Ruby: Reorganize mapping of componentsNilay Vaish
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for mapping MachineType to GenericMachineType. These '#define's are being eliminated and the code will now be generated by SLICC instead. Also are being eliminated some of the unused functions from RubySlicc_ComponentMapping.sm.
2011-10-22SE: move page allocation from PageTable to ProcessSteve Reinhardt
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process.
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