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mem
Age
Commit message (
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Author
2016-05-26
mem: fix the line length in the cache related classes
Nikos Nikoleris
2016-04-26
ruby: Rename pkt to m_pkt so it may be accessed via SLICC
Matthew Poremba
2016-04-21
mem: Include WriteLineReq in cache demand stats
Andreas Hansson
2016-04-21
mem: Remove unused cache stats
Andreas Hansson
2016-04-21
mem: Deallocate all write-queue entries when sent
Andreas Hansson
2016-04-21
mem: Align downstream cache packet creation in atomic and timing
Andreas Hansson
2016-04-15
ruby: Fix block_on behavior
Joel Hestness
2016-04-15
mem: FreeBSD does not provide MAP_NORESERVE either
Bjoern A. Zeeb
2016-04-13
misc: Fix issues flagged by gcc 6
Andreas Hansson
2016-04-07
mem: Add priority to QueuedPrefetcher
Rekai Gonzalez Alberquilla
2016-04-07
mem: Handful extra features for BasePrefetcher
Rekai Gonzalez Alberquilla
2016-04-07
mem: Add Program Counter to MemTraceProbe
Victor Garcia
2015-05-27
mem: Add unused prefetch counter in caches
Rekai Gonzalez Alberquilla
2016-04-07
mem: Remove threadId from memory request class
Mitch Hayenga
2016-04-07
Revert to 74c1e6513bd0 (sim: Thermal support for Linux)
Andreas Sandberg
2016-04-06
Revert power patch sets with unexpected interactions
Andreas Sandberg
2016-04-05
mem: Remove threadId from memory request class
Mitch Hayenga
2014-11-18
power: Add power states to ClockedObject
Akash Bagdia
2016-03-17
mem: Adjust cache queue reserve to more conservative values
Andreas Hansson
2016-03-17
mem: Create a separate class for the cache write buffer
Andreas Hansson
2015-08-10
mem, cpu: Add assertions to snoop invalidation logic
Stephan Diestelhorst
2016-02-24
mem: Ensure that InvalidateReq is not forwarded as ReadExReq
Andreas Hansson
2016-02-23
scons: Add missing override to appease clang
Andreas Hansson
2016-02-18
ruby: move range change send from RubyPort to derived classes.
Tony Gutierrez
2016-02-17
ruby: send address ranges from RubyPort
Tony Gutierrez
2016-02-15
misc: Add missing overrides to appease clang
Andreas Hansson
2016-02-15
mem: Avoid using invalid iterator in cache lock list traversal
Andreas Hansson
2016-02-14
ruby: make DMASequencer inherit from RubyPort
Michael LeBeane
2016-02-10
mem: Be less conservative in clearing load locks in the cache
Andreas Hansson
2016-02-10
mem: Move the point of coherency to the coherent crossbar
Andreas Hansson
2016-02-10
mem: Align cache behaviour in atomic when upstream is responding
Andreas Hansson
2016-02-10
mem: Align how snoops are handled when hitting writebacks
Andreas Hansson
2016-02-10
mem: Deduce if cache should forward snoops
Andreas Hansson
2016-02-06
style: eliminate explicit boolean comparisons
Steve Reinhardt
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2016-02-06
style: remove trailing whitespace
Steve Reinhardt
2016-01-22
ruby: removed Write_Only AccessPermission
Brad Beckmann
2015-07-20
ruby: split CPU and GPU latency stats
David Hashe
2016-01-19
gpu-compute: AMD's baseline GPU model
Tony Gutierrez
2016-01-19
mem: write combining for ruby protocols
Tony Gutierrez
2016-01-19
* * *
Tony Gutierrez
2015-07-20
mem: misc flags for AMD gpu model
Blake Hechtman
2016-01-11
mem: fix bug in packet access endianness changes
Steve Reinhardt
2016-01-11
scons: Enable -Wextra by default
Andreas Hansson
2015-12-31
mem: add CacheVerbose debug flag, filter noisy DPRINTFs
Steve Reinhardt
2015-12-31
mem: Do not rely on the NeedsWritable flag for responses
Andreas Hansson
2015-12-31
mem: Do not allocate space for packet data if not needed
Andreas Hansson
2015-12-31
mem: Do not alter cache block state on uncacheable snoops
Andreas Hansson
2015-12-31
mem: Make cache terminology easier to understand
Andreas Hansson
2015-07-20
ruby: slicc: have a static MachineType
Tony Gutierrez
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