gem5 - gem5

Age	Commit message (Expand)	Author
2014-06-30	mem: DRAMPower trace output	Andreas Hansson
2014-06-30	mem: Add bank and rank indices as fields to the DRAM bank	Andreas Hansson
2014-06-30	mem: Extend DRAM row bits from 16 to 32 for larger densities	Andreas Hansson
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-05-23	ruby: slicc: remove unused ids DNUCA*	Nilay Vaish
2014-05-23	ruby: remove old protocol documentation	Nilay Vaish
2014-05-23	ruby: message buffer: drop dequeue_getDelayCycles()	Nilay Vaish
2014-05-09	mem: Update DDR3 and DDR4 based on datasheets	Andreas Hansson
2014-05-09	mem: Add DRAM cycle time	Andreas Hansson
2014-05-09	mem: Simplify DRAM response scheduling	Andreas Hansson
2014-05-09	mem: Add precharge all (PREA) to the DRAM controller	Andreas Hansson
2014-05-09	mem: Remove printing of DRAM params	Andreas Hansson
2014-05-09	mem: Add tRTP to the DRAM controller	Andreas Hansson
2014-05-09	mem: Merge DRAM latency calculation and bank state update	Andreas Hansson
2014-05-09	mem: Add tWR to DRAM activate and precharge constraints	Andreas Hansson
2014-05-09	mem: Merge DRAM page-management calculations	Andreas Hansson
2014-05-09	mem: Add DRAM power states to the controller	Andreas Hansson
2014-05-09	mem: Ensure DRAM refresh respects timings	Andreas Hansson
2014-05-09	mem: Make DRAM read/write switching less conservative	Andreas Hansson
2014-05-09	mem: Squash prefetch requests from downstream caches	Mitch Hayenga
2014-05-09	mem: Auto-generate CommMonitor trace file names	Sascha Bischoff
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-04-19	ruby: slicc: remove old documentation	Nilay Vaish
2014-04-19	ruby: slicc: slight change to rule for transitions	Nilay Vaish
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-04-08	ruby: slicc: change enqueue statement	Nilay Vaish
2014-04-08	ruby: coherence protocols: drop the phrase IntraChip	Nilay Vaish
2014-03-23	mem: Track DRAM read/write switching and add hysteresis	Andreas Hansson
2014-03-23	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	Andreas Hansson
2014-03-23	mem: Change memory defaults to be more representative	Andreas Hansson
2014-03-23	mem: Add close adaptive paging policy to DRAM controller model	Wendy Elsasser
2014-03-23	mem: DRAM controller tidying up	Andreas Hansson
2014-03-23	mem: Fix bug in DRAM bytes per activate	Andreas Hansson
2014-03-23	mem: Limit the accesses to a page before forcing a precharge	Andreas Hansson
2014-03-23	mem: Make DRAM write queue draining more aggressive	Andreas Hansson
2014-03-23	mem: DDR3 config for comparing with DRAMSim2	Neha Agarwal
2014-03-23	mem: More descriptive address-mapping scheme names	Andreas Hansson
2014-03-23	ruby: Move Ruby debug flags to ruby dir and remove stale options	Andreas Hansson
2014-03-23	mem: Include the DRAMSim2 wrapper in NULL build	Andreas Hansson
2014-03-23	mem: CommMonitor trace warn on non-timing mode	Sascha Bischoff
2014-03-20	ruby: consumer: avoid accessing wakeup times when waking up	Nilay Vaish
2014-03-20	ruby: garnet: convert network interfaces into clocked objects	Nilay Vaish
2014-03-20	ruby: slicc: code refactor	Nilay Vaish
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-03-07	mem: Fix incorrect assert failure in the Cache	Prakash Ramrakhyani
2014-03-07	mem: Wakeup sleeping CPUs without caches on LLSC	Ali Saidi
2014-03-01	ruby: message buffer: changes related to tracking push/pop times	Nilay Vaish
2014-03-01	ruby: make the max_size variable of the MessageBuffer unsigned	Nilay Vaish
2014-03-01	ruby: profiler: statically allocate stats variable	Nilay Vaish