summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2014-07-25mem: Add missig timing and current parameters to DRAM configsOmar Naji
2014-10-09mem: Remove DRAMSim2 DDR3 configurationOmar Naji
2014-10-09mem: Add packet sanity checks to cache and MSHRsAndreas Hansson
2014-10-09mem: Allow packet queue to move next send event forwardAndreas Hansson
2014-10-01misc: Fix issues identified by static analysisAndreas Hansson
2014-09-27mem: Output precise range when XBar has conflictsCurtis Dunham
2014-09-27mem: Provide better diagnostic for unconnected portCurtis Dunham
2014-09-27misc: Fix a bunch of minor issues identified by static analysisAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-04-25mem: Add access statistics for the snoop filterStephan Diestelhorst
2014-09-20mem: Tie in the snoop filter in the coherent busStephan Diestelhorst
2014-04-24mem: Add a simple snoop counter per busStephan Diestelhorst
2014-09-20mem: Simple Snoop FilterStephan Diestelhorst
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-09-20mem: Remove the GHB prefetcher from the source treeMitch Hayenga
2014-09-19misc: Use safe_cast when assumptions are made about return valueAndreas Hansson
2014-09-19misc: Remove assertions ensuring unsigned values >= 0Andreas Hansson
2014-09-19mem: Check return value of checkFunctional in SimpleMemoryAndreas Hansson
2014-09-19mem: Add checks to sendTimingReq in cacheAndreas Hansson
2014-09-15ruby: network: revert some of the changes from ad9c042dce54Nilay Vaish
2014-09-09mem: Add accessor function for vaddrMitch Hayenga
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-09-03base: Use the global Mersenne twister throughoutAndreas Hansson
2014-09-03mem: Avoid unecessary retries when bus peer is not readyAndreas Hansson
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-05-13cpu, mem: Make software prefetches non-blockingCurtis Dunham
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cache: Fix handling of LL/SC requests under contentionGeoffrey Blake
2014-09-03mem: Packet queue clean upAndreas Hansson
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-09-01ruby: remove typedef of Index as int64Nilay Vaish
2014-09-01ruby: PerfectSwitch: moves code to a per vnet helper functionNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01build opts: add MI_example to NULL ISANilay Vaish
2014-09-01mem: change the namespace Message to ProtoMessageNilay Vaish
2014-09-01ruby: slicc: change the way configurable members are specifiedNilay Vaish
2014-09-01ruby: slicc: improve the grammarNilay Vaish
2014-09-01ruby: mesi three level: slight naming changes.Nilay Vaish
2014-09-01ruby: slicc: donot prefix machine name to variablesNilay Vaish
2014-09-01ruby: remove unused toString() from AbstractControllerNilay Vaish
2014-09-01ruby: network: move getNumNodes() to base classNilay Vaish
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-09-01ruby: move files from ruby/system to ruby/structuresNilay Vaish
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-04-01mem: adding a multi-level page table classAlexandru
2014-08-26mem: Fix DRAMSim2 cycle check when restoring from checkpointAndreas Hansson
2014-08-26mem: Update DRAM controller commentsAndreas Hansson
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson