gem5 - gem5

Age	Commit message (Expand)	Author
2013-09-06	ruby: network: removes reset functionality	Nilay Vaish
2013-09-06	ruby: network: shorten variable names	Nilay Vaish
2013-09-06	ruby: converts sparse memory stats to gem5 style	Nilay Vaish
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-08-19	stats: Cumulative stats update	Andreas Hansson
2013-08-19	config: Command line support for multi-channel memory	Andreas Hansson
2013-08-19	mem: Change AbstractMemory defaults to match the common case	Andreas Hansson
2013-08-19	mem: Use STL deque in favour of list for DRAM queues	Andreas Hansson
2013-08-19	mem: Perform write merging in the DRAM write queue	Andreas Hansson
2013-08-19	mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM	Amin Farmahini
2013-08-19	mem: Warn instead of panic for tXAW violation	Andreas Hansson
2013-08-19	mem: Allow disabling of tXAW through a 0 activation limit	Andreas Hansson
2013-08-19	mem: Add an internal packet queue in SimpleMemory	Andreas Hansson
2013-08-07	ruby: slicc: remove double trigger, continueProcessing	Nilay Vaish
2013-08-07	ruby: slicc: move some code to AbstractController	Nilay Vaish
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-07-11	ruby: removed the very old double trigger hack	Brad Beckmann
2013-06-28	ruby: append transition comment only when in opt/debug	Nilay Vaish
2013-06-28	ruby: network: remove reconfiguration code	Nilay Vaish
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-27	mem: Tidy up the bridge with const and additional checks	Andreas Hansson
2013-06-27	mem: Fix CommMonitor style and response check	Andreas Hansson
2013-06-27	mem: Align cache timing to clock edges	Andreas Hansson
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-06-27	mem: Remove a redundant heap allocation for a snoop packet	Andreas Hansson
2013-06-27	mem: Remove CoherentBus snoop port unused private member	Andreas Hansson
2013-06-25	ruby: moesi cmp directory: separate actions for external hits	Nilay Vaish
2013-06-25	ruby: mesi cmp directory: separate actions for external hits	Nilay Vaish
2013-06-25	ruby: profiler: lots of inter-related changes	Nilay Vaish
2013-06-24	ruby: remove the three files related to profiling	Nilay Vaish
2013-06-24	ruby: MessageBuffer: Remove unused m_size variable	Joel Hestness ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-06-20	ruby: fix typo in MOESI_CMP_token protocol	Lena Olson
2013-06-18	ruby: Fix prefetching for MESI_CMP_Directory	Lena Olson
2013-06-18	ruby: fix slicc compiler to complain about duplicate symbols	Lena Olson
2013-06-18	ruby: restrict Address to being a type and not a variable name	Lena Olson
2013-06-18	kvm: Use the address finalization code in the TLB	Andreas Sandberg
2013-06-09	ruby: remove several unused variables in Profiler	Nilay Vaish
2013-06-09	ruby: remove periodic event from Profiler	Nilay Vaish
2013-06-09	ruby: stats: use gem5's stats for cache and memory controllers	Nilay Vaish
2013-06-09	ruby: remove undefined functions in Address class	Nilay Vaish
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-05-30	mem: Make returning snoop responses occupy response layer	Andreas Hansson