Age | Commit message (Expand) | Author |
2013-02-10 | ruby: Replace Time with Cycles in SequencerMessage | Nilay Vaish |
2013-02-10 | ruby: replace Time with Cycles in Message class | Nilay Vaish |
2013-02-10 | ruby: replaces Time with Cycles in many places | Nilay Vaish |
2013-02-10 | ruby: modifies histogram add() function | Nilay Vaish |
2013-02-10 | ruby: record fully busy cycle with in the controller | Nilay Vaish |
2013-01-31 | ruby: correct computation of number of bits required for address | Nilay Vaish |
2013-01-31 | mem: Add comments for the DRAM address decoding | Andreas Hansson |
2013-01-31 | mem: Add DDR3 and LPDDR2 DRAM controller configurations | Andreas Hansson |
2013-01-31 | mem: Add tTAW and tFAW to the SimpleDRAM model | Ani Udipi |
2013-01-31 | mem: Separate out the different cases for DRAM bus busy time | Andreas Hansson |
2013-01-28 | cache: remove drainManager because it's not used | Anthony Gutierrez |
2013-01-28 | ruby: remove get_time() | Nilay Vaish |
2013-01-28 | ruby: remove call to curCycle in panic() | Nilay Vaish |
2013-01-17 | ruby: remove calls to g_system_ptr->getTime() | Nilay Vaish |
2013-01-14 | ruby sequencer: converts cycles to ticks in deadlock panic() | Malek Musleh |
2013-01-14 | Ruby: remove reference to g_system_ptr from class Message | Nilay Vaish |
2013-01-14 | Ruby: use ClockedObject in Consumer class | Nilay Vaish |
2013-01-08 | mem: Make LL/SC locks fine grained | Mitch Hayenga |
2013-01-08 | mem: Fix use-after-free bug | Mitch Hayenga |
2013-01-07 | mem: Fix guest corruption when caches handle uncacheable accesses | Andreas Sandberg |
2013-01-07 | mem: Remove the IIC replacement policy | Andreas Sandberg |
2013-01-07 | sim: Fatal if a clocked object is set to have a clock of 0 | Andreas Hansson |
2013-01-07 | mem: Merge ranges that are part of the conf table | Andreas Hansson |
2013-01-07 | mem: Add interleaving bits to the address ranges | Andreas Hansson |
2013-01-07 | base: Simplify the AddrRangeMap by removing unused code | Andreas Hansson |
2013-01-07 | mem: Tidy up bus addr range debug messages | Andreas Hansson |
2013-01-07 | mem: Skip address mapper range checks to allow more flexibility | Andreas Hansson |
2013-01-07 | base: Encapsulate the underlying fields in AddrRange | Andreas Hansson |
2013-01-07 | mem: Remove the joining of neighbouring ranges | Andreas Hansson |
2013-01-07 | mem: Add tracing support in the communication monitor | Andreas Hansson |
2013-01-07 | mem: Add sanity check to packet queue size | Andreas Hansson |
2013-01-07 | ruby: Fix missing cxx_header in Switch | Andreas Hansson |
2013-01-07 | mem: Fix a bug in the memory serialization file naming | Andreas Hansson |
2013-01-07 | cache: add note about where conflicts are handled | Ali Saidi |
2012-12-11 | ruby: add support for prefetching to MESI protocol | Nilay Vaish |
2012-12-11 | ruby: change slicc to allow for constructor args | Nilay Vaish |
2012-12-11 | ruby: add a prefetcher | Nilay Vaish |
2012-12-11 | ruby: add functions for computing next stride/page address | Nilay Vaish |
2012-11-16 | sim: have a curTick per eventq | Nilay Vaish |
2012-11-10 | ruby: support functional accesses in garnet flexible network | Nilay Vaish |
2012-11-10 | ruby: bug in functionalRead, revert recent changes | Nilay Vaish |
2012-11-08 | mem: Fix DRAM draining to ensure write queue is empty | Andreas Hansson |
2012-11-02 | ruby: reset and dump stats along with reset of the system | Hamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) |
2012-11-02 | mem: fix use after free issue in memories until 4-phase work complete. | Ali Saidi |
2012-11-02 | mem: Add support for writing back and flushing caches | Andreas Sandberg |
2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
2012-11-02 | ARM: dump stats and process info on context switches | Dam Sunwoo |
2012-10-31 | mem: Fix typo in port comments | Andreas Hansson |
2012-10-25 | dev: Make default clock more reasonable for system and devices | Andreas Hansson |