gem5 - gem5

Age	Commit message (Expand)	Author
2014-11-06	ruby: provide a backing store	Nilay Vaish
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: remove the function functionalReadBuffers()	Nilay Vaish
2014-11-06	ruby: coherence protocols: remove data block from dirctory entry	Nilay Vaish
2014-11-06	ruby: slicc: allow adding a bool to an int, like C++.	Nilay Vaish
2014-11-06	ruby: remove sparse memory.	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-11-06	ruby: dma sequencer: remove RubyPort as parent class	Nilay Vaish
2014-10-29	arm, mem: Fix drain bug and provide drain prints for more components.	Ali Saidi
2014-10-21	mem: don't inhibit WriteInv's or defer snoops on their MSHRs	Curtis Dunham
2014-10-29	mem: have WriteInvalidate obsolete MSHRs	Curtis Dunham
2014-10-20	mem: Fix DRAM activationlLimit bug	Omar Naji
2014-10-20	mem: Add DRAM device size and check against config	Omar Naji
2014-10-16	mem: Modernise PhysicalMemory with C++11 features	Andreas Hansson
2014-10-16	misc: Move AddrRangeList from port.hh to addr_range.hh	Andreas Hansson
2014-10-16	mem: Add ExternalMaster and ExternalSlave ports	Andrew Bardsley
2014-10-16	mem: Use shared_ptr for Ruby Message classes	Andreas Hansson
2014-10-16	arch,x86,mem: Dynamically determine the ISA for Ruby store check	Andreas Hansson
2014-10-16	mem: Dynamically determine page bytes in memory components	Andreas Hansson
2014-10-11	ruby: network: garnet: add statistics for different activities	Nilay Vaish
2014-10-11	ruby: network: garnet: remove functions for computing power	Nilay Vaish
2014-10-11	ruby: drop Orion network power model	Nilay Vaish
2014-10-11	ruby: mesi: slight renaming	Nilay Vaish
2014-10-11	ruby: structures: coorect #ifndef macros in header files	Nilay Vaish
2014-07-29	mem: DRAMPower integration for on-line DRAM power stats	Omar Naji
2014-07-29	mem: Add DRAMPower wrapping class	Omar Naji
2014-07-25	mem: Add missig timing and current parameters to DRAM configs	Omar Naji
2014-10-09	mem: Remove DRAMSim2 DDR3 configuration	Omar Naji
2014-10-09	mem: Add packet sanity checks to cache and MSHRs	Andreas Hansson
2014-10-09	mem: Allow packet queue to move next send event forward	Andreas Hansson
2014-10-01	misc: Fix issues identified by static analysis	Andreas Hansson
2014-09-27	mem: Output precise range when XBar has conflicts	Curtis Dunham
2014-09-27	mem: Provide better diagnostic for unconnected port	Curtis Dunham
2014-09-27	misc: Fix a bunch of minor issues identified by static analysis	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-04-25	mem: Add access statistics for the snoop filter	Stephan Diestelhorst
2014-09-20	mem: Tie in the snoop filter in the coherent bus	Stephan Diestelhorst
2014-04-24	mem: Add a simple snoop counter per bus	Stephan Diestelhorst
2014-09-20	mem: Simple Snoop Filter	Stephan Diestelhorst
2014-09-20	mem: Add DDR4 bank group timing	Wendy Elsasser
2014-09-20	mem: Add memory rank-to-rank delay	Wendy Elsasser
2014-09-20	mem: Remove the GHB prefetcher from the source tree	Mitch Hayenga
2014-09-19	misc: Use safe_cast when assumptions are made about return value	Andreas Hansson
2014-09-19	misc: Remove assertions ensuring unsigned values >= 0	Andreas Hansson
2014-09-19	mem: Check return value of checkFunctional in SimpleMemory	Andreas Hansson
2014-09-19	mem: Add checks to sendTimingReq in cache	Andreas Hansson
2014-09-15	ruby: network: revert some of the changes from ad9c042dce54	Nilay Vaish
2014-09-09	mem: Add accessor function for vaddr	Mitch Hayenga
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-09-03	base: Use the global Mersenne twister throughout	Andreas Hansson