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mem
Age
Commit message (
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Author
2012-08-01
Ruby NetDest: add assert for bad element in netdest
Jason Power
2012-07-27
cache: don't allow dirty data in the i-cache
Anthony Gutierrez
2012-07-23
Bridge: Use EventWrapper instead of Event subclass for sendEvent
Andreas Hansson
2012-07-12
Mem: Make SimpleMemory single ported
Andreas Hansson
2012-07-12
Ruby: remove config information from ruby.stats
Nilay Vaish
2012-07-12
Ruby: remove some unused stuff from SLICC files
Nilay Vaish
2012-07-11
ruby: improved DRAM reset comment
Brad Beckmann
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
# User Brad Beckmann <Brad.Beckmann@amd.com>
Brad Beckmann
2012-07-10
imported patch jason/slicc-external-structure-fix
Brad Beckmann
2012-07-10
ruby: banked cache array resource model
Brad Beckmann
2012-07-10
ruby: tag and data cache access support
Joel Hestness
2012-07-10
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena
2012-07-10
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Nuwan Jayasena
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-07-09
Mem: Make members relating to range and size constant
Andreas Hansson
2012-07-09
Port: Hide the queue implementation in SimpleTimingPort
Andreas Hansson
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Bus: Make the default bus width 8 bytes instead of 64
Andreas Hansson
2012-07-09
Bus: Split the bus into separate request/response layers
Andreas Hansson
2012-07-09
Bus: Add a notion of layers to the buses
Andreas Hansson
2012-07-09
Bus: Replace tickNextIdle and inRetry with a state variable
Andreas Hansson
2012-07-09
Port: Make getAddrRanges const
Andreas Hansson
2012-07-09
Port: Add getAddrRanges to master port (asking slave port)
Andreas Hansson
2012-07-09
Port: Add isSnooping to slave port (asking master port)
Andreas Hansson
2012-07-09
Port: Move retry from port base class to Master/SlavePort
Andreas Hansson
2012-07-09
Fix: Address a few benign memory leaks
Andreas Hansson
2012-06-29
Cache: Fix the LRU policy for classic memory hierarchy
Lena Olson
2012-06-29
Bus: enable non/coherent buses sub-classes
Uri Wiener
2012-06-29
Mem: fix master id assertion in cache_impl.hh
Dam Sunwoo
2012-06-29
Mem: Fix a livelock resulting in LLSC/locked memory access implementation.
Matt Evans
2012-06-29
Cache: Only invalidate a line in the cache when an uncacheable write is seen.
Ali Saidi
2012-06-07
mem: Delay deleting of incoming packets by one call.
Ali Saidi
2012-06-05
Mem: add per-master stats to physmem
Dam Sunwoo
2012-06-05
sim: Remove FastAlloc
Ali Saidi
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-05-30
Bus: Remove redundant packet parameter from isOccupied
Andreas Hansson
2012-05-30
Bus: Turn the PortId into a transport function parameter
Andreas Hansson
2012-05-30
Packet: Unify the use of PortID in packet and port
Andreas Hansson
2012-05-30
Packet: Updated comments for src and dest fields
Andreas Hansson
2012-05-30
Bridge: Split deferred request, response and sender state
Andreas Hansson
2012-05-24
Cache: Remove dangling doWriteback declaration
Andreas Hansson
2012-05-23
Packet: Cleaning up packet command and attribute
Andreas Hansson
2012-05-22
Ruby: Remove the unused src/mem/ruby/common/Driver.* files.
Nilay Vaish
2012-05-22
Ruby Sequencer: Schedule deadlock check event at correct time
Nilay Vaish
2012-05-10
mem: fix bug with CopyStringOut and null string termination.
Ali Saidi
2012-05-10
Cache: restructure code that actually isn't a loop
Ali Saidi
2012-05-10
gem5: assert before indexing intro arrays to verify bounds
Ali Saidi
2012-05-10
gem5: fix some iterator use and erase bugs
Ali Saidi
2012-05-10
gem5: Fix a number of incorrect case statements
Ali Saidi
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