gem5 - gem5

Age	Commit message (Expand)	Author
2012-09-05	Ruby Memory Controller: Fix clocking	Joel Hestness
2012-08-28	Ruby: Correct DataBlock =operator	Jason Power
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Port: Stricter port bind/unbind semantics	Andreas Hansson
2012-08-27	Ruby: remove README.debugging and Decommissioning_note	Nilay Vaish
2012-08-27	Ruby: Remove RubyEventQueue	Nilay Vaish
2012-08-27	Ruby Memory Vector: Allow more than 4GB of memory	Nilay Vaish
2012-08-25	MESI Protocol: Correct the virtual network in profile functions	Nilay Vaish
2012-08-25	MESI Coherence Protocol: Add copyright notice	Nilay Vaish
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-08-21	PacketQueue: Allow queuing in the same tick as desired send tick	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-19	Ruby Banked Array: add copyrights	Nilay Vaish
2012-08-16	Ruby: Add RubySystem parameter to MemoryControl	Jason Power
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-10	Ruby: Clean up topology changes	Jason Power
2012-08-06	SETranslatingPortProxy: fix bug in tryReadString()	Steve Reinhardt
2012-08-01	Ruby NetDest: add assert for bad element in netdest	Jason Power
2012-07-27	cache: don't allow dirty data in the i-cache	Anthony Gutierrez
2012-07-23	Bridge: Use EventWrapper instead of Event subclass for sendEvent	Andreas Hansson
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-07-12	Ruby: remove config information from ruby.stats	Nilay Vaish
2012-07-12	Ruby: remove some unused stuff from SLICC files	Nilay Vaish
2012-07-11	ruby: improved DRAM reset comment	Brad Beckmann
2012-07-10	# User Brad Beckmann <Brad.Beckmann@amd.com>	Brad Beckmann
2012-07-10	# User Brad Beckmann <Brad.Beckmann@amd.com>	Brad Beckmann
2012-07-10	imported patch jason/slicc-external-structure-fix	Brad Beckmann
2012-07-10	ruby: banked cache array resource model	Brad Beckmann
2012-07-10	ruby: tag and data cache access support	Joel Hestness
2012-07-10	ruby: adds reset function to Ruby memory controllers	Nuwan Jayasena
2012-07-10	ruby: memory controllers now inherit from an abstract "MemoryControl" class	Nuwan Jayasena
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-07-09	Mem: Make members relating to range and size constant	Andreas Hansson
2012-07-09	Port: Hide the queue implementation in SimpleTimingPort	Andreas Hansson
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Bus: Make the default bus width 8 bytes instead of 64	Andreas Hansson
2012-07-09	Bus: Split the bus into separate request/response layers	Andreas Hansson
2012-07-09	Bus: Add a notion of layers to the buses	Andreas Hansson
2012-07-09	Bus: Replace tickNextIdle and inRetry with a state variable	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Port: Add getAddrRanges to master port (asking slave port)	Andreas Hansson
2012-07-09	Port: Add isSnooping to slave port (asking master port)	Andreas Hansson
2012-07-09	Port: Move retry from port base class to Master/SlavePort	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	Cache: Fix the LRU policy for classic memory hierarchy	Lena Olson
2012-06-29	Bus: enable non/coherent buses sub-classes	Uri Wiener
2012-06-29	Mem: fix master id assertion in cache_impl.hh	Dam Sunwoo
2012-06-29	Mem: Fix a livelock resulting in LLSC/locked memory access implementation.	Matt Evans