Age | Commit message (Expand) | Author |
2014-09-19 | misc: Use safe_cast when assumptions are made about return value | Andreas Hansson |
2014-09-19 | misc: Remove assertions ensuring unsigned values >= 0 | Andreas Hansson |
2014-09-19 | mem: Check return value of checkFunctional in SimpleMemory | Andreas Hansson |
2014-09-19 | mem: Add checks to sendTimingReq in cache | Andreas Hansson |
2014-09-15 | ruby: network: revert some of the changes from ad9c042dce54 | Nilay Vaish |
2014-09-09 | mem: Add accessor function for vaddr | Mitch Hayenga |
2014-09-09 | misc: Fix a number of unitialised variables and members | Andreas Hansson |
2014-09-03 | base: Use the global Mersenne twister throughout | Andreas Hansson |
2014-09-03 | mem: Avoid unecessary retries when bus peer is not ready | Andreas Hansson |
2014-06-27 | mem: write streaming support via WriteInvalidate promotion | Curtis Dunham |
2014-09-03 | mem: Fix a bug in the cache port flow control | Andreas Hansson |
2014-05-13 | cpu, mem: Make software prefetches non-blocking | Curtis Dunham |
2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
2014-09-03 | cache: Fix handling of LL/SC requests under contention | Geoffrey Blake |
2014-09-03 | mem: Packet queue clean up | Andreas Hansson |
2014-09-03 | arch: Cleanup unused ISA traits constants | Andreas Hansson |
2014-09-01 | ruby: remove typedef of Index as int64 | Nilay Vaish |
2014-09-01 | ruby: PerfectSwitch: moves code to a per vnet helper function | Nilay Vaish |
2014-09-01 | ruby: message buffers: significant changes | Nilay Vaish |
2014-09-01 | build opts: add MI_example to NULL ISA | Nilay Vaish |
2014-09-01 | mem: change the namespace Message to ProtoMessage | Nilay Vaish |
2014-09-01 | ruby: slicc: change the way configurable members are specified | Nilay Vaish |
2014-09-01 | ruby: slicc: improve the grammar | Nilay Vaish |
2014-09-01 | ruby: mesi three level: slight naming changes. | Nilay Vaish |
2014-09-01 | ruby: slicc: donot prefix machine name to variables | Nilay Vaish |
2014-09-01 | ruby: remove unused toString() from AbstractController | Nilay Vaish |
2014-09-01 | ruby: network: move getNumNodes() to base class | Nilay Vaish |
2014-09-01 | ruby: eliminate type Time | Nilay Vaish |
2014-09-01 | ruby: move files from ruby/system to ruby/structures | Nilay Vaish |
2014-08-28 | mem: adding architectural page table support for SE mode | Alexandru |
2014-04-01 | mem: adding a multi-level page table class | Alexandru |
2014-08-26 | mem: Fix DRAMSim2 cycle check when restoring from checkpoint | Andreas Hansson |
2014-08-26 | mem: Update DRAM controller comments | Andreas Hansson |
2014-08-26 | mem: Fix address interleaving bug in DRAM controller | Andreas Hansson |
2014-08-13 | mem: Properly set cache block status fields on writebacks | Mitch Hayenga |
2014-07-28 | mem: refactor LRU cache tags and add random replacement tags | Anthony Gutierrez |
2014-06-30 | mem: DRAMPower trace output | Andreas Hansson |
2014-06-30 | mem: Add bank and rank indices as fields to the DRAM bank | Andreas Hansson |
2014-06-30 | mem: Extend DRAM row bits from 16 to 32 for larger densities | Andreas Hansson |
2014-05-31 | style: eliminate equality tests with true and false | Steve Reinhardt |
2014-05-23 | ruby: slicc: remove unused ids DNUCA* | Nilay Vaish |
2014-05-23 | ruby: remove old protocol documentation | Nilay Vaish |
2014-05-23 | ruby: message buffer: drop dequeue_getDelayCycles() | Nilay Vaish |
2014-05-09 | mem: Update DDR3 and DDR4 based on datasheets | Andreas Hansson |
2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
2014-05-09 | mem: Simplify DRAM response scheduling | Andreas Hansson |
2014-05-09 | mem: Add precharge all (PREA) to the DRAM controller | Andreas Hansson |
2014-05-09 | mem: Remove printing of DRAM params | Andreas Hansson |
2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
2014-05-09 | mem: Merge DRAM latency calculation and bank state update | Andreas Hansson |